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LPC4350 Dataheets PDF



Part Number LPC4350
Manufacturers NXP
Logo NXP
Description 32-bit ARM Cortex-M4/M0 MCU
Datasheet LPC4350 DatasheetLPC4350 Datasheet (PDF)

LPC435x/3x/2x/1x 32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 5.4 — 10 January 2020 Product data sheet 1. General description The LPC435X_3X_2X_1X are ARM Cortex-M4 based microcontrollers with Floating Point Unit (FPU) for embedded applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, two high-speed USB controllers, Ethernet, LCD, an external memory control.

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LPC435x/3x/2x/1x 32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 5.4 — 10 January 2020 Product data sheet 1. General description The LPC435X_3X_2X_1X are ARM Cortex-M4 based microcontrollers with Floating Point Unit (FPU) for embedded applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and 136 kB of on-chip SRAM, 16 kB of EEPROM memory, two high-speed USB controllers, Ethernet, LCD, an external memory controller, a quad SPI Flash Interface (SPIFI) that supports execute-in-place, advanced configurable peripherals such as the State Configurable Timer (SCTimer/PWM) and the Serial General Purpose I/O (SGPIO) interface, and multiple digital and analog peripherals. The LPC435X_3X_2X_1X operate at CPU frequencies of up to 204 MHz. The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point processor is integrated into the core. The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core, which is upward code- and tool-compatible with the Cortex-M4 core. It is ideal for handling control or peripheral handling to free up the Cortex-M4 for real-time processing. The Cortex-M0 coprocessor offers up to 204 MHz performance with a simple instruction set and reduced code size. In LPC43xx, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative multiplier. For additional documentation related to the LPC43xx parts, see Section 17. 2. Features and benefits  Cortex-M4 Processor core  ARM Cortex-M4 processor (version r0p1), running at frequencies of up to 204 MHz.  Built-in Memory Protection Unit (MPU) supporting eight regions.  Built-in Nested Vectored Interrupt Controller (NVIC).  Hardware floating-point unit.  Non-maskable Interrupt (NMI) input.  JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.  Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.  System tick timer. NXP Semiconductors LPC435x/3x/2x/1x 32-bit ARM Cortex-M4/M0 microcontroller  Cortex-M0 Processor core  ARM Cortex-M0 co-processor (version r0p0) capable of off-loading the main ARM Cortex-M4 application processor.  Running at frequencies of up to 204 MHz.  JTAG  Built-in NVIC.  On-chip memory  Up to 1 MB on-chip dual bank flash memory with flash accelerator.  16 kB on-chip EEPROM data memory.  136 kB SRAM for code and data use.  Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.  64 kB ROM containing boot code and on-chip software drivers.  64 bit+ 256 bit of One-Time Programmable (OTP) memory for general-purpose use.  Configurable digital peripherals  Serial GPIO (SGPIO) interface.  State Configurable Timer (SCTimer/PWM) subsystem on AHB.  Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.  Serial interfaces  Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.  10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time stamping (IEEE 1588-2008 v2).  One High-speed USB 2.0 Host/Device/OTG interface with DMA support and on-chip high-speed PHY.  One High-speed USB 2.0 Host/Device interface with DMA support, on-chip full-speed PHY and ULPI interface to external high-speed PHY.  USB interface electrical test software included in ROM USB stack.  One 550 UART with DMA support and full modem interface.  Three 550 USARTs with DMA and synchronous mode support and a smart card interface conforming to ISO7816 specification. One USART with IrDA interface.  Up to two C_CAN 2.0B controllers with one channel each.  Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA support.  One SPI controller.  One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O pins conforming to the full I2C-bus specification. Supports data rates of up to 1 Mbit/s.  One standard I2C-bus interface with monitor mode and with standard I/O pins.  Two I2S interfaces, each with DMA support and with one input and one output.  Digital peripherals  External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash, and SDRAM devices. LPC435X_3X_2X_1X Product data sheet All information provided in this document.


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