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High Voltage, Fractional-N/ Integer-N PLL Synthesizer ADF4150HV
FEATURES
Fractional-N synthesizer and integer-N synthesizer High voltage charge pump: VP = 6 V to 30 V Tuning range: 1.0 V to 29 V (or ±1 V from VP supply rails) RF bandwidth to 3.0 GHz Programmable divide-by-1/-2/-4/-8/-16 outputs Synthesizer power supply: 3.0 V to 3.6 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level Programmable charge pump currents RF output mute function 3-wire serial interface Analog and digital lock detect
GENERAL DESCRIPTION
The ADF4150HV is a 3.0 GHz, fractional-N or integer-N frequency synthesizer with an integrated high voltage charge pump. The synthesizer can be used to drive external wideband VCOs directly, eliminating the need for operational amplifiers to achieve higher tuning voltages. This simplifies design and reduces cost while improving phase noise, in contrast to active filter topologies, which tend to degrade phase noise compared to passive filter topologies. The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable. A simple 3-wire interface controls all on-chip registers. The charge pump operates from a power supply ranging from 6 V to 30 V, whereas the rest of the device operates from 3.0 V to 3.6 V. The ADF4150HV can be powered down when not in use.
APPLICATIONS
Wireless infrastructure Microwave point-to-point/point-to-multipoint radios VSAT radios Test equipment Private land mobile radios
FUNCTIONAL BLOCK DIAGRAM
SDVDD AVDD DVDD VP RSET
REFIN
×2 DOUBLER
10-BIT R COUNTER
÷2 DIVIDER LOCK DETECT
MULTIPLEXER
MUXOUT LD
CLK DATA LE
DATA REGISTER
FUNCTION LATCH PHASE COMPARATOR
HIGH VOLTAGE CHARGE PUMP BOOST MODE
CPOUT
CURRENT SETTING DIVIDE-BY-1/ -2/-4/-8/-16
INTEGER VALUE
FRACTION VALUE
MODULUS VALUE
OUTPUT STAGE
RFOUT+ RFOUT– PDBRF
THIRD-ORDER FRACTIONAL INTERPOLATOR
MULTIPLEXER
RF INPUT
RFIN+ RFIN–
N COUNTER
CE
GND
CPGND
SDGND
Figure 1.
Rev. 0
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09058-001
Free Datasheet http://www.datasheet4u.com/
ADF4150HV
ADF4150HV TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 6 Transistor Count ........................................................................... 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 Circuit Description ......................................................................... 11 Reference Input Section ............................................................. 11 RF N Divider ............................................................................... 11 Phase Frequency Detector (PFD) and High Voltage Charge Pump .............................................................................. 11 MUXOUT and Lock Detect ...................................................... 12 Input Shift Registers ................................................................... 12 Program Modes .......................................................................... 12 Output Stage ................................................................................ 12 Register Maps .........................................................................