Document
UBA2013/L3
HB driver IC with PFC for fluorescent rings
Rev. 00.01 — 23 February 2007 Preliminary data sheet
1. General description
The UBA2013/L3 is a high voltage IC intended to drive and control fluorescent lamps. The IC can handle both cold and warm ignition of the lamp. It contains a TON-controlled PFC function, a half bridge controller circuit with level shifter and an internal bootstrap diode to drive an external half bridge. UBA2013/L3 also offers a functionality to properly handle fault conditions such as capacitive mode switching, end-of-lamp-life and overcurrent. UBA2013/L3 is designed for wide-input mains voltage (120 V - 277 V) applications.
2. Features
2.1 Half bridge
Suitable for cold and warm ignition Adjustable preheat time Adjustable ignition voltage Integrated bootstrap function Protection for lamp failure and end-of-life Adjustable preheat current Single ignition attempt Automatic restart after relamping Protection for capacitive mode
2.2 PFC
Three pin PFC controller using TON control Critical mode operation Overvoltage/overcurrent protection
3. Applications
The UBA2013/L3 can provide the drive and control function for a wide range of half bridge based ballast applications at different mains voltages.
4. Ordering information
Table 1. Ordering information Package Name UBA2013T SO16 Description plastic small outline package; 16 leads; body width 3.9mm Version SOT109-1 Type number
Free Datasheet http://www.datasheet4u.com/
5. Block diagram
FS LEVELSHIFTER HIGH SIDE DRIVER G1 S1
BOOTSTRAP
VDD
NONOVERLAP
SUPPLY
BANDGAP
LOW SIDE DRIVER
G2
GZCD
CONTROL
TIMING
CP
VO
PFC
STOP
STOP
OVC
RS MON
RS
OSCILLATOR
EOL
EOL
UBA2013
RREF CF CI GND
014aaa042
Fig 1. Block diagram of UBA2013/L3
Free Datasheet http://www.datasheet4u.com/
6. Pinning information
6.1 Pinning
VO OVC CF CI CP EOL RREF STOP
1 2 3 4
16 GZCD 15 GND 14 VDD 13 G2
UBA2013
5 6 7 8 12 RS 11 G1 10 FS 9 S1
014aaa044
Fig 2. Pin configuration for UBA2013/L3
6.2 Pin description
Table 2. Symbol VO OVC CF CI CP EOL RREF STOP S1 FS G1 RS G2 VDD GND GZCD Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description PFC output voltage sensing PFC overvoltage/current Oscillator capacitor Integrating capacitor Timing capacitor End-of-life Reference resistor Stop Source high side transistor (T1) High side floating supply Gate high side transistor (T1) Current sensor Gate low side transistor (T2) Low voltage supply Ground PFC gate and ZCD
Free Datasheet http://www.datasheet4u.com/
7. Functional description
7.1 Start-up state
Initial start up can be achieved by means of charging the VDD low voltage supply capacitor (C2 in the application diagram Figure 6) via an external start-up resistor. Start-up state is one of the non-oscillating sub-states. MOSFET T2 conducts and T1 is non-conducting, ensuring bootstrap capacitor C3 to be charged. In this state the circuit will be reset. The GZCD pin is pulled down and IVO(ref) is not active. If VSTOP < VSTOP(reset) at the transition of VDD exceeding VDD(start), the IC will enter the oscillating state. If not it will enter the stop state.
7.2 Half bridge oscillator
Oscillation of the half bridge is controlled by a built-in current-controlled oscillator which generates a sawtooth waveform at the CF pin. The sawtooth frequency is twice the half bridge frequency, and is determined by the capacitor at the CF pin and the current-out of pin CF, as controlled by the voltage at the CI pin. Frequency modulation is achieved by charging and discharging the CI capacitor. The IC brings MOSFETs T1 and T2 alternately into conduction with a duty factor of just below 50% each (except for situations where VRS exceeds VRS(clamp)). Figure 3 represents the timing of the IC. The circuit block ‘non-overlap’ generates a non-overlap time tno that ensures periods of exclusive conduction of T1 or T2. Time tno depends on the reference current IRREF.
7.3 Oscillating state
Oscillating state can be entered:
• when in the startup state VSTOP < VSTOP(reset) at the moment VDD reaches VDD(start), • when in the VddLow state, when VSTOP < VSTOP(ref) at the moment VDD reaches
VDD(start). The oscillating state has three sub-states: the preheat state, the ignition state and the burn state. The circuit always starts oscillating in the preheat state.
VCF
internal clock
VG1_S1
VG2
TNO
TNO
014aaa044
Fig 3. Oscillator timing
Free Datasheet http://www.datasheet4u.com/
7.4 Preheat state
The circuit starts oscillating at the half-bridge frequency fstart (approximately 2.5 x fB). The frequency gradually decreases until a user-defined value of the preheat current is reached. The slope of the decrease in frequency is determined by the capacitor at the CI pin. During preheat, the circuit monitors the inductor current by measuring the voltage across external resistor RS at the end of the conduction of T2 with decision level VRS(ph). The frequency is decreased for as long as VRS < VRS(.