CPU Supervidor. X4643 Datasheet

X4643 Datasheet PDF, Equivalent


Part Number

X4643

Description

(X4643 / X4645) CPU Supervidor

Manufacture

Intersil

Total Page 21 Pages
PDF Download
Download X4643 Datasheet


X4643 Datasheet
®
Data Sheet
March 29, 2005
X4643, X4645
64K, 8K x 8 Bit
FN8123.0
CPU Supervisor with 64K EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Four standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog off
—3mA active current
• 64Kbits of EEPROM
—64-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC
—8-lead TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X4643/5 combines four popular functions, Power-
on Reset Control, Watchdog Timer, Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the RESET/RESET
signal. The user selects the interval from three preset
values. Once selected, the interval does not change,
even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when VCC falls below the set minimum
VCC trip point. RESET/RESET is asserted until VCC
returns to proper operating level and stabilizes. Four
industry standard VTRIP thresholds are available,
however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or
to fine-tune the threshold for applications requiring
higher precision.
WP
SDA
SCL
S0
S1
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset Logic
Protect Logic
Status
Register
EEPROM Array
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
RESET (X4643/5)
RESET (X4645)
VCC
+
Power-on and
Low Voltage
VTRIP
-
Reset
Generation
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
Free Datasheet http://www.datasheet4u.com/

X4643 Datasheet
X4643, X4645
PIN CONFIGURATION
8-Pin JEDEC SOIC
S0
S1
RESET/RESET
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8 Pin TSSOP
WP
VCC
S0
S1
1
2
3
4
8 SCL
7 SDA
6 VSS
5 RESET/RESET
PIN FUNCTION
Pin
(SOIC)
1
2
3
4
5
6
7
8
Pin
(TSSOP)
3
4
5
6
7
8
1
2
Name
S0
S1
RESET/RESET
VSS
SDA
SCL
WP
VCC
Function
Device Select Input
Device Select Input
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
which goes active whenever VCC falls below the minimum VCC sense level. It
will remain active until VCC rises above the minimum VCC sense level for
250ms. RESET/RESET goes active if the Watchdog Timer is enabled and SDA
remains either HIGH or LOW longer than the selectable Watchdog time out pe-
riod. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer.
RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open
drain or open collector outputs. This pin requires a pull up resistor and the input
buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) re-
starts the Watchdog timer. The absence of a HIGH to LOW transition within the
watchdog time out period results in RESET/RESET going active.
Serial Clock. The Serial Clock controls the serial bus timing for data input and
output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
Supply Voltage
2 FN8123.0
March 29, 2005
Free Datasheet http://www.datasheet4u.com/


Features Datasheet pdf ® X4643, X4645 64K, 8K x 8 Bit Data Sh eet March 29, 2005 FN8123.0 CPU Superv isor with 64K EEPROM FEATURES • Selec table watchdog timer • Low VCC detect ion and reset assertion —Four standar d reset threshold voltages —Adjust lo w VCC reset threshold voltage using spe cial programming sequence —Reset sign al valid to VCC = 1V • Low power CMOS —<20µA max standby current, watchdo g on —<1µA standby current, watchdog off —3mA active current • 64Kbits of EEPROM —64-byte page write mode Self-timed write cycle —5ms write cy cle time (typical) • Built-in inadver tent write protection —Power-up/power -down protection circuitry • 400kHz 2 -wire interface • 2.7V to 5.5V power supply operation • Available packages —8-lead SOIC —8-lead TSSOP DESCRI PTION The X4643/5 combines four popular functions, Poweron Reset Control, Watc hdog Timer, Supply Voltage Supervision, and Serial EEPROM Memory in one packag e. This combination lowers system cost, reduces board space requirements, and increases reliability. Apply.
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