SDRAM. IC42S81600L Datasheet

IC42S81600L Datasheet PDF


Part

IC42S81600L

Description

4M x 8M x 4 Banks SDRAM

Manufacture

Integrated Circuit Solution

Page 30 Pages
Datasheet
Download IC42S81600L Datasheet


IC42S81600L Datasheet
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
Document Title
4(2)M x 8(16) Bit x 4 Banks (128-MBIT) SDRAM
Revision History
Revision No
History
0A Initial Draft
0B Corrected typo on PIN FUNCTIONS and
revise DC OPERATING CONDITIONS
0C Append two parameters tDPL ,tDAL;correct tRCD
and tRP and modify DC operating condition
0D 1.Obsolete speed grade -7H
2.Support Pb-free package
3.Modify typo in page 16,17
0E Add Industrial range
Change ICC5 from 160mA to 180mA
Draft Date
August 27,2001
May 6,2002
Remark
August 21,2003
September 09,2003
June 11,2004
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
1

IC42S81600L Datasheet
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
4(2)M x 8(16) Bits x 4 Banks (128-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
• Single 3.3V (± 0.3V) power supply
• High speed clock cycle time -6: 166MHz<3-3-3>,
-7H: 133MHz<2-2-2>, -7: 133MHz<3-3-3>, -8:
100MHz<2-2-2>
• Fully synchronous operation referenced to clock
rising edge
• Possible to assert random column access in
every cycle
• Quad internal banks contorlled by BA0 & BA1
(Bank Select)
• Byte control by LDQM and UDQM for
IC42S16800
• Programmable Wrap sequence (Sequential /
Interleave)
• Programmable burst length (1, 2, 4, 8 and full
page)
• Programmable CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge
command
• Package 400mil 54-pin TSOP-2
DESCRIPTION
The IC42S81600 and IC42S16800 are high-speed
134,217,728-bit synchronous dynamic random-
access memories, organized as 4,194,304 x 8 x 4 and
2,097,152 x 16 x 4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data
transfer using the pipeline architecture. All input and
outputs are synchronized with the positive edge of the
clock.The synchronous DRAMs are compatible with
Low Voltage TTL (LVTTL).These products are pack-
aged in 54-pin TSOP-2.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
DR023-0E 6/11/2004


Features Datasheet pdf IC42S81600/IC42S81600L IC42S16800/IC42S1 6800L Document Title 4(2)M x 8(16) Bit x 4 Banks (128-MBIT) SDRAM Revision Hi story Revision No 0A 0B 0C 0D 0E Histo ry Initial Draft Corrected typo on PIN FUNCTIONS and revise DC OPERATING CONDI TIONS Append two parameters tDPL ,tDAL; correct tRCD and tRP and modify DC oper ating condition 1.Obsolete speed grade -7H 2.Support Pb-free package 3.Modify typo in page 16,17 Add Industrial range Change ICC5 from 160mA to 180mA Draft Date August 27,2001 May 6,2002 August 21,2003 Remark September 09,2003 June 11,2004 The attached datasheets are p rovided by ICSI. Integrated Circuit Sol ution Inc reserve the right to change t he specifications and products. ICSI wi ll answer to your questions about devic e. If you have any questions, please co ntact the ICSI offices. Integrated Cir cuit Solution Inc. DR023-0E 6/11/2004 1 IC42S81600/IC42S81600L IC42S16800/IC 42S16800L 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Single 3.3V (± 0.
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