Document
HIP0063
PRELIMINARY
October 1995
Hex Low Side MOSFET Driver with Serial or Parallel Interface and Diagnostic Fault Control
Description
The HIP0063 is a logic controlled, six channel Low Side Power Driver. As shown in the Block Diagram, the outputs are controlled via the serial data interface or, by user option, each output may be independently controlled from the respective parallel input. In addition, PWM logic switching control (HLOS) may be directly applied to channels 0 and 1 in parallel, or channels 4 and 5 in parallel. Output fault conditions may be detected as an output load short to supply when the output is ON or as an open load/ground short when the output is OFF. If an over-current short exists at one output, gate drive goes to a low duty cycle mode. It will remain in the low duty cycle mode until switched off or the fault is cleared. Fault bits are sent to a fault register to indicate which channel is at fault. The fault bits are indicated by a logic one and is internally latched when CS goes low. A fault bit will return to zero when the fault disappears. Either an 8-bit or 16-bit SPI communication mode may be used. Refer to the application section for bit control information. Over-voltage shutdown protection for all outputs will occur when VPWR (Battery/ MOSFET Supply) exceeds 35V typical. When VCC is less than 3.5V, gate drive is switched off. The input and gate control logic is fully function when the VCC supply is greater than 4V typical. The HIP0063 has an internal drain-to-gate zener which is used to voltage clamp the output drain-to-source voltage of the MOSFET. The HIP0063 is fabricated in a Power BiMOS IC process, and is intended for use in automotive and other applications having a wide range of temperature and electrical stress conditions. It is particularly well suited for MOSFET control in circuits driving lamps, displays, relays, and solenoids in applications requiring low operating power.
Features
• Six Channel MOSFET Driver with Gate Drive Control by Serial (SPI) or Parallel Interface and an Option for PWM Logic Switching Control • Drain Monitor Provides Fault Detection and Voltage Clamp for Each Channel • Output Voltage Zener Clamp. . . . . . . . . . 67V Typ • 5V CMOS Logic Level Input Control • VCC Logic Level Power Supply - 5V VCC Logic Power Supply - Turns Off Gate Drive for Low or Loss of VCC • VPWR System Level Power Supply Management - 5.5V to 17V Battery/System Level Power Supply Monitor - Over-Voltage Shutdown . . . . . . . . . . . . 35V Typ • Output Supply/Load Short and Open Load/Ground Short Fault Detection • Automatic Change to Low Duty Cycle Drive Mode When Output Short-to-Supply Detected • Fault Diagnostic Feedback via the SPI Bus • Operating Temp Range . . . . . . . -40oC to +125oC
Applications
• • • • Automotive and Industrial Systems Control of Solenoids, Relays and Lamp Drivers Interface to Logic and µP Controllers Robotic System Controller
Ordering Information
PART NUMBER HIP0063AB TEMPERATURE RANGE -40oC to +125oC PACKAGE 28 Lead Plastic SOIC (W)
Pinout
HIP0063 SOIC TOP VIEW
HLOS 1 HPW01 2 HPW45 3 P10 4 P11 5 P12 6 P13 7 P14 8 P15 9 CS 10 SO 11 SI 12 SCK 13 GND 14 28 VPWR 27 G0 26 D0 25 G1 24 D1 23 D2 22 G2 21 G3 20 D3 19 D4 18 G4 17 D5 16 G5 15 VCC
Block Diagram
+VPWR
VPWR VCC
OVSD +5V POR
CHANNEL#0 - (1 OF 6) FAULT LOGIC AND LATCH F0 FAULT DATA OVSD TG GATE CONTROL LOGIC
D0 (DRAIN MONITOR VOLT,VDM) G0 (GATE DR. VOLT.,VG) GND
HPW01 HPW45 HLOS CS SI SO SCK PI0-5
MUX PWM CONTROL S0 S6 P0 SPI (SER.) CONTROL S0-5 F0-5 (6) PI0-5
TG
POR HIP0063
OSC AND TIME DELAY CONTROL
EXT POWER MOSFET AND TYP LOAD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
4009
1
HIP0063
VCC 5V
VPWR 14V
S0 SI SCK CS
SPI
POR, TIMING OSC, BAND GAP REF., OVER-VOLT. DET.
VPWR (VBATT) 14V D0 G0 D1 G1 D2 G2 D3 G3 D4 G4 D5 G5
PI0
PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL PARALLEL/ SERIAL IN, SHIFT REG. CONTROL
DATA LATCH
DRAIN MONITOR DRIVE CONTROL CHANNEL #0 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #1 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #2 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #3 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #4 GATE DRIVER DRAIN MONITOR DRIVE CONTROL CHANNEL #5 GATE DRIVER HIP0063
PI1
DATA LATCH
PARALLEL INPUTS
PI2
DATA LATCH
PI3
DATA LATCH
PI4
DATA LATCH
PI5
DATA LATCH
HLOS (SEL) HPW01 HPW45
HLOS
GND HARDWARE GENERATED OR CUSTOM LOGIC SOURCED PWM CONTROL SIGNAL INPUTS
2 - HIP0061 OR EQUIVALENT
FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING HOW THE GATE DRIVE OUTPUT AND DRAIN MONITOR INPUT CONTROLS TWO HIP0061 THREE FET ARRAYS
CS
SCK (CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
INT.