Document
HIP6500
Data Sheet December 1999 File Number 4774.1
Multiple Linear Power Controller with ACPI Control Interface
The HIP6500 complements either an HIP6020 or an HIP6021 in ACPI-compliant designs for microprocessor and computer applications. The IC integrates two linear controllers and two regulators, switching, monitoring and control functions into a 20-pin SOIC package. One linear controller generates the 3.3VDUAL voltage plane from the ATX supply’s 5VSB output, powering the PCI slots through an external pass transistor during sleep states (S3, S4/S5). A second transistor is used to switch in the ATX 3.3V output for operation during S0 and S1/S2 (active) operating states. The second linear controller supplies the computer system’s 2.5V/3.3V memory power through an external pass transistor in active states. During S3 state, an integrated pass transistor supplies the 2.5V/3.3V sleep power. A third controller powers up the 5VDUAL plane by switching in the ATX 5V output in active states, and the ATX 5VSB in sleep states. The two internal regulators consist of a low current 3.3V sleep output and a dedicated, noise-free 2.5V clock chip supply. The HIP6500’s operating mode (active outputs or sleep outputs) is selectable through two digital control pins, S3 and S5. Further control of the logic governing activation of different power states is offered through two configuration pins, EN3VDL and EN5VDL. In active state, the 3.3VDUAL linear regulator uses an external N-Channel pass MOSFET to connect the output directly to the 3.3V input supplied by an ATX (or equivalent) power supply, for minimal losses. In sleep state, power delivery on the 3.3VDUAL output is transferred to an NPN transistor, also external to the controller. Active state power delivery for the 2.5/3.3VMEM output is performed through an external NPN transistor, or an NMOS switch for the 3.3V setting. In sleep state, conduction on this output is transferred to an internal pass transistor. The 5VDUAL output is powered through two external MOS transistors. In sleep states, a PMOS (or PNP) transistor conducts the current from the ATX 5VSB output; while in active state, current flow is transferred to an NMOS transistor connected to the ATX 5V output. Similar to the 3.3VDUAL output, the operation of the 5VDUAL output is dictated not only by the status of the S3 and S5 pins, but that of the EN5VDL pin as well. The 3.3VSB internal regulator is active for as long as the ATX 5VSB voltage is applied to the chip, and derives its output current from the 5VSB pin. The 2.5VCLK output is only active during S0 and S1/S2, and uses the 3V3 pin as input source for its internal pass element.
Features
• Provides 5 ACPI-Controlled Voltages - 5V Active/Sleep (5VDUAL) - 3.3V Active/Sleep (3.3VDUAL) - 2.5V/3.3V Active/Sleep (2.5VMEM) - 3.3V Always Present (3.3VSB) - 2.5V Clock (Active Only) (2.5VCLK) • Excellent Output Voltage Regulation - 3.3VDUAL Output: ±2.0% Over Temperature; Sleep State Only - 2.5V/3.3VMEM Output: ±2.0% Over Temperature; Both Operational States (3.3V setting in sleep only) - 2.5VCLK and 3.3VSB Output: ±2.0% Over Temperature • Small Size - Very Low External Component Count • Selectable Memory Output Voltage Via FAULT/MSEL Pin - 2.5V for RDRAM Memory - 3.3V for SDRAM Memory • Under-Voltage Monitoring of All Outputs with Centralized FAULT Reporting and Temperature Shutdown
Applications
• Motherboard Power Regulation for ACPI-Compliant Computers
Pinout
HIP6500 (SOIC) TOP VIEW
20 EN3VDL 19 DRV2 18 5V 17 12V 16 SS 15 5VDL 14 5VDLSB 13 DLA 12 FAULT/MSEL 11 GND
VSEN2
1
5VSB 2 3V3SB 3 3V3DLSB 4 3V3DL 5 VCLK 6 3V3 7 EN5VDL S3 8 9
S5 10
Ordering Information
PART NUMBER HIP6500CB HIP6500EVAL1 TEMP. RANGE (oC) 0 to 70 PACKAGE 20 Ld SOIC PKG. NO. M20.3
Evaluation Board
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Block Diagram
12V 3V3DLSB 3V3DL 5V 3V3 5VSB 5VDLSB DLA
EA4 + 12V MONITOR 10.2V/9.2V + 3.75V 5VDL UV COMPARATOR
5VSB POR 4.5V/4.0V TEMPERATURE MONITOR (TMON)
TO 5VSB
EA3
+
3V3SB TO UV DETECTOR MONITOR AND CONTROL + TO UV DETECTOR EA3 TO 3V3
FAULT/MSEL
UV DETECTOR
TO 5VSB 40µA + 10µA TO UV DETECTOR EA2
-
GND
SS
2
S3 S5 EN3VDL EN5VDL
HIP6500
VCLK
+ 1.265V
TO 5V
DRV2
+
VSEN2
FIGURE 1.
HIP6500 Simplified Power System Diagram
+5VIN +12VIN +5VSB +3.3VIN 3.3VSB 3.3V Q2 3.3VDUAL 3.3V FAULT/MSEL Q3 LINEAR CONTROLLER LINEAR REGULATOR LINEAR CONTROLLER Q1 VMEM 2.5V/3.3V VCLK 2.5V Q5 5VDUAL 5V SHUTDOWN SX ENXVDL 2 2 Q4
LINEAR REGULATOR
HIP6500
CONTROL LOGIC
FIGURE 2.
Typical Application
+5VIN +12VIN +5VSB +3.3VIN
12V VOUT1 3.3VSB COUT1 5V 3V3DLSB 3V3SB
3V3
5VSB
DRV2 VSEN2
Q1
Q2 Q3 VOUT3 3.3VDUAL COUT3
VOUT2 2.5/3.3VMEM
COUT2 3V3DL FAULT/MSEL VCLK VOUT4
HIP6500
FAULT RSEL
2.5VCLK COUT4 Q4
5VDLSB SLP_S3 SLP_S5 EN5VDL EN3VDL S3 S5 EN5VDL EN3VDL SS CSS SHUTDOWN GND 5VDL COUT5 DLA Q5 VOUT5 5VDUAL
FI.