DatasheetsPDF.com

HMP151F7EFR4C-S5 Dataheets PDF



Part Number HMP151F7EFR4C-S5
Manufacturers Hynix
Logo Hynix
Description 240pin Fully Buffered DDR2 SDRAM DIMMs
Datasheet HMP151F7EFR4C-S5 DatasheetHMP151F7EFR4C-S5 Datasheet (PDF)

240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb E-ver. This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SD.

  HMP151F7EFR4C-S5   HMP151F7EFR4C-S5


Document
240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb E-ver. This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point Link Interface at 1.5V power. The AMB also allows buffering of memory traffic to support large memory capacities. All memory control for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access and power management. The AMB interface is responsible for handling channel and memory requests to and from the local FBDIMM and for forwarding request to other FBDIMMs on the memory channel. FEATURES • • • • • • • • • • • • • • • • • 240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Built with 1Gb DDR2 SDRAMs in 60ball FBGA Host interface and AMB component industry standard compliant MBIST, IBIST test functions 8 Bank architecture OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM 133.35 x 30.35 mm form factor RoHS compliant Full DIMM Heat Spreader This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Sep. 2008 1 Free Datasheet http://www.datasheet4u.com/ 1240pin Fully Buffered DDR2 SDRAM DIMMs ORDERING INFORMATION Part Name HMP112F7EFR8C-Y5N3 HMP112F7EFR8C-Y5/S5/S6D3 HMP112F7EFR8C-Y5/S5/S6D5 HMP125F7EFR8C-Y5N3 HMP125F7EFR8C-Y5/S5/S6D3 HMP125F7EFR8C-Y5/S5/S6D5 HMP151F7EFR4C-Y5N3 HMP151F7EFR4C-Y5/S5/S6D3 HMP151F7EFR4C-Y5/S5/S6D5 HMP151F7EFR8C-Y5/S5/S6D5 HMP31GF7EMR4C-Y5/S5/S6D5 4GB 8GB 512Mx72 1Gx72 36 72 4 4 4GB 512Mx72 36 2 2GB 256Mx72 18 2 1GB 128Mx72 9 1 Density Org. # of DRAMs # of ranks AMB Vendor Intel IDT Intel IDT Intel IDT IDT Version D1 C1 AMB+ D1 C1 AMB+ D1 C1 AMB+ AMB+ AMB+ Full Module 30.35mm H. S type Height Note *: The 17th and 18th digits stand for AMB vendor and revision. **: ‘R’ of Part Number;11th digit, stands for lead & Halogen free products. ***: Intel AMB for H/F is under development SPEED GRADE & KEY PARAMETERS Speed Grade DDR2 DRAM Speed Grade FB-DIMM Speed Grade FB-DIMM Peak Channel Throughput FB-DIMM Link Transfer Rate Y5 DDR2 667 5-5-5 PC2 5300 8.0 4.0 S5/6 DDR2 800 5-5-5 / 6-6-6 PC2 6400 9.6 4.8 GByte/S GT/s Unit ADDRESS TABLE Density 1GB 2GB 4GB 4GB 8GB Organization 128M x 72 256M x 72 512M x 72 512M x 72 1G x 72 Ranks 1 2 2 4 4 SDRAMs 128Mbx8 128Mbx8 256Mbx4 128Mbx8 256Mbx4 # of DRAMs 9 18 36 36 72 # of row/bank/column Address 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 14(A0~A13)/3(BA0~BA2)/11(A0~A9,A11) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms 8K / 64ms Rev. 0.2 / Sep. 2008 2 Free Datasheet http://www.datasheet4u.com/ 1240pin Fully Buffered DDR2 SDRAM DIMMs Input/Output Functional Description Pin Name SCK SCK PN[13:0] PN[13:0] PS[9:0] PS[9:0] SN[13:0] SN[13:0] SS[9:0] SS[9:0] SCL SDA SA[2:0] VID[1:0] RESET RFU VCC VDD VTT VDDSPD VSS type Input Input Output Output Input Input Output Output Input Input Input Input / Output Input Input Input Supply Supply Supply Supply Supply Polarity Positive Negative Positive Negative Positive Negative Positive Negative Positive Negative Active Low +1.5V +1.8V +0.9V +3.3V System clock input System clock input Primary Northbound Data Primary Northbound Data Primary Southbound Data Primary Southbound Data Secondary Northbound Data Secondary Northbound Data Secondary Southbound Data Secondary Southbound Data Serial Presence Detect (SPD) Clock Input SPD Data Input / Output SPD Address inputs, also used to select the DIMM number in the AMB Voltage ID: These pins must be unconnected for DDR2-based Fully buffered DIMMs AMB reset signal Reserved for Future Use AMB Core Power and AMB channel Interface Power(1.5volt) DRAM Power and AMB DRAM I/O Power DRAM Address/Command/Clock Termination Power(VDD/2) SPD Power Ground The DNU/M_Test pin provides an external connection on R/Cs A-D for testing the margin of Vref which is produced by a voltage divider on .


HMP151F7EFR4C-Y5 HMP151F7EFR4C-S5 HMP151F7EFR4C-S6D3


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)