ADSP-BF607

Blackfin Dual Core Embedded Processor ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609 FEATURES Dual-core symmetric high-performance Blackfin processor, up to 500 MHz per core Each core contains two 16-bit MACs, two 40-bit ALUs, and a 40-bit barrel shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Pipelined Vision Processor provides hardware to process signal and image algorithms used for pre- and co-processing of video frames in ADAS or other video processing applications Accepts a range of supply voltages for I/O operation. See Operating Conditions on Page 52 Off-chip voltage regulator interface 349-ball BGA package (19 mm × 19 mm), RoHS compliant MEMORY Each core contains 148K bytes of L1 SRAM memory (processor core-accessible) with multi-parity bit protection Up to 256K bytes of L2 SRAM memory with ECC protection Dynamic memory controller provides 16-bit interface to a single bank of DDR2 or LPDDR DRAM devices Static memory controller with asynchronous memory inter- face that supports 8-bit and 16-bit memories 4 Memory-to-memory DMA streams, 2 of which feature CRC protection Flexible booting options from flash, SD EMMC, and SPI mem- ories and from SPI, link port and UART hosts Memory management unit provides memory protection EMULATOR TEST & CONTROL PLL & POWER MANAGEMENT FAULT MANAGEMENT SYSTEM CONTROL BLOCKS EVENT CONTROL DUAL WATCHDOG PERIPHERALS 2× TWI 8× TIMER ...