Document
3851 Group (Built-in 24 KB or more ROM)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0066-0101Z Rev.1.01 Oct 15, 2003
DESCRIPTION
The 3851 group (built-in 24 KB or more ROM) is the 8-bit microcomputer based on the 740 family core technology. The 3851 group (built-in 24 KB or more ROM) is designed for the household products and office automation equipment and includes serial I/O functions, 8-bit timer, I2C-BUS interface, and A-D converter.
FEATURES
Basic machine-language instructions ..................................... 71 Minimum instruction execution time ................................. 0.5 µs (at 8 MHz oscillation frequency) Memory size ROM ................................................................ 24K to 32K bytes RAM .................................................................... 640 to 1K bytes Programmable input/output ports ........................................... 34 Interrupts ................................................ 17 sources, 16 vectors Timers ............................................................................ 8-bit X 4 Serial I/O1 .................... 8-bit X 1(UART or Clock-synchronized) Serial I/O2 ................................... 8-bit X 1(Clock-synchronized) Multi-master I2C-BUS interface .................................. 1 channel PWM .............................................................................. 8-bit X 1 A-D converter ............................................... 10-bit X 5 channels Watchdog timer ........................................................... 16-bit X 1
Clock generating circuit ................................... Built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode ................................................. 4.0 to 5.5 V (at 8 MHz oscillation frequency) In middle-speed mode ............................................. 2.7 to 5.5 V (at 8 MHz oscillation frequency) In low-speed mode ................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency) Power dissipation In high-speed mode ......................................................... 34 mW (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode Except M38517F8FP/SP ................................................. 60 µW M38517F8FP/SP ............................................................ 450 µW (at 32 kHz oscillation frequency, at 3 V power source voltage) Operating temperature range .................................. –20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products, Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
VCC VREF AVSS P44/INT3/PWM P43/INT2/SCMP2 P42/INT1 P41/INT0 P40/CNTR1 P27/CNTR0/SRDY1 P26/SCLK1 P25/SCL2/TxD P24/SDA2/RxD P23/SCL1 P22/SDA1 CNVSS P21/XCIN P20/XCOUT RESET XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P30/AN0 P31/AN1 P32/AN2 P33/AN3 P34/AN4 P00/SIN2 P01/SOUT2 P02/SCLK2 P03/SRDY2 P04 P05 P06 P07 P10/(LED0) P11/(LED1) P12/(LED2) P13/(LED3) P14/(LED4) P15/(LED5) P16/(LED6) P17/(LED7)
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP) Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38517M8-XXXFP/SP pin configuration
M38517M8-XXXFP/SP
Rev.1.01
Oct 15, 2003
page 1 of 89
Free Datasheet http://www.datasheet4u.com/
FUNCTIONAL BLOCK
Rev.1.01
Reset input VSS VCC
1 15 18 21
FUNCTIONAL BLOCK DIAGRAM
Main-clock input XIN RESET CNVSS
Main-clock output XOUT
Fig.2 Functional block diagram
3851 Group (Built-in 24 KB or more ROM)
Oct 15, 2003
C P U
19
20
Sub-clock Sub-clock input output XCIN XCOUT
Clock generating circuit
page 2 of 89
ROM
X
Prescaler 12(8)
RAM
Timer 2( 8 ) Timer X( 8 ) Timer Y( 8 ) Y
Prescaler X(8)
A
Timer 1( 8 )
S PC H PS
CNTR1
PC L
Prescaler Y(8)
CNTR0
Watchdog timer
Reset
A-D converter (10)
PWM (8)
SI/O1(8)
I2C
SI/O2(8)
XCOUT INT0– INT3 XCIN
P4(5)
P3(5)
P2(8)
P1(8)
P0(8)
2 3 38 39 40 41 42
4 5 6 7 8
9 10 11 12 13 1416 17
22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37
I/O port P4 I/O port P3
I/O port P2
I/O port P1
I/O port P0
VREF
AVSS
Free Datasheet http://www.datasheet4u.com/
3851 Group (Built-in 24 KB or more ROM)
Table 1 Pin description Pin VCC, VSS CNVSS VREF AVSS RESET XIN XOUT Name Power source CNVSS input Reference voltage input Analog power source input Reset input Clock input Clock output Functions •Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. •This pin controls the operation mode of the chip. •Normally connected to VSS. •Reference voltage input pin for A-D converter. •Analog power source input pin for A-D converter. •Connect to Vss. •Reset input pin for active “L”. •Input and output pins for the clock generating circuit. •Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the.