RainboW-G17M-Q7

Cyclone V SoC Qseven Module System On Module RainboW-G17M-Q7 SPECIFICATIONS CPU: Qseven PCB Edge Connector Interfaces: iW-RainboW-G17M-Q7 HIGHLIGHTS From HPS: Gigabit Ethernet - 1 Port (On-SOM PHY) USB 2.0 Host - 4 Ports (On-SOM HUB) CAN - 1 Port FPGA with upto 110K LEs # SD/MMC (8 bit) Memory: WDOG - 1 Port I2C - 2 Ports 16MB QSPI Flash # SPI - 1 Port On-SOM Micro SD Connector Debug UART - 1 Port 256MB DDR3 for FPGA 2nd UART - 1 Port EPCQ Flash* / QSPI Flash for FPGA Other Control IOs - Through HPS + From FPGA : On Board Peripherals Support: LVDS LCD - 2 Ports (FPGA Soft IP)/ 23 SE IOs JTAG Header for FPGA* AC97/I2S Audio (FPGA Soft IP)/ 5 SE IOs PWM FPGA IOs - 8 SE IOs + From FPGA High Speed Transceivers : 80 Pin Expansion Connector: FPGA IOs (Up to 45 Single Ended IOs - SE IOs): PCIe Gen1 x 4 Lane SATA (FPGA Soft IP) 9 TX LVDS Pairs / 18 SE IOs Form Factor: 11 RX LVDS Pairs / 22 SE IOs 70mm x 70mm Qseven Specification 2.0 5 Single Ended IOs Altera’s Cyclone V SX SoC FPGA Integrated Dual core ARM Cortex-A9 Hard Processor System(HPS) FPGA Dedicated Clock IOs: General Purpose Clock Inputs (2 LVDS/2 SE) General Purpose Clock Outputs (1 LVDS/2 SE) Others: SMBUS / 2 SE IOs FPGA JTAG * Optional # + Power Input: 5V DC Operating Temperature: -40oC to +85oC Industrial Operating System: WEC7, Linux On-SOM Micro SD Connector and Qseven Edge SD/MMC are sharing the same interface If the FPGA interfaces available in the Qseven edge are not used for Qseven compliance requirement...