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TP80C51BH Dataheets PDF



Part Number TP80C51BH
Manufacturers Intel
Logo Intel
Description (TP8xCx1BH) CMOS Single-Chip 8-Bit Microcontroller
Datasheet TP80C51BH DatasheetTP80C51BH Datasheet (PDF)

87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH *See Table 1 for Proliferation Options ■ ■ ■ High Performance CHMOS EPROM 24 MHz Operation Improved Quick-Pulse Programming Algorithm 3-Level Program Memory Lock Boolean Processor 128-Byte Data RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Extended Temperature Range (- 40°C to + 85 ° C) ■ ■ ■ 5 Interrupt Sources Programmable Serial Port TTL- and CMOS-Compatible Logic Level.

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87C51/80C51BH/80C31BH CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express 87C51/80C51BH/80C51BHP/80C31BH *See Table 1 for Proliferation Options ■ ■ ■ High Performance CHMOS EPROM 24 MHz Operation Improved Quick-Pulse Programming Algorithm 3-Level Program Memory Lock Boolean Processor 128-Byte Data RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Extended Temperature Range (- 40°C to + 85 ° C) ■ ■ ■ 5 Interrupt Sources Programmable Serial Port TTL- and CMOS-Compatible Logic Levels 64K External Program Memory Space 64K External Data Memory Space ONCE Mode Facilitates System Testing Power Control Modes • Idle • Power Down ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ MEMORY ORGANIZATION PROGRAM MEMORY: Up to 4 Kbytes of the program memory can reside on-chip (except 80C31BH). In addition the device can address up to 64K of program memory external to the chip. DATA MEMORY: This microcontroller has a 128 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of external data memory. The Intel 87C51/80C51BH/80C31BH is a single-chip control-oriented microcontroller which is fabricated on Intel's reliable CHMOS III-E technology. Being a member of the MCS® 51 controller family, the 87C51/80C51BH/80C31BH uses the same powerful instruction set, has the same architecture, and is pin-forpin compatible with the existing MCS 51 controller family of products. The 80C51BHP is identical to the 80C51BH. When ordering the 80C51BHP, customers must submit the 64 byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code protection and at the same time allows code verification. The extremely low operating power, along with the two reduced power modes, Idle and Power Down, make this part very suitable for low power applications. The Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. For the remainder of this document, the 87C51, 80C51BH, and 80C31BH will be referred to as the 87C51/BH, unless information applies to a specific device. * Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 2004 July 2004 Order Number: 272335-004 87C51/80C51BH/80C31BH Table 1. Proliferation Options Standard 80C31BH 80C51BH 80C51BHP 87C51 NOTES: 3.5 MHz -1 3.5 MHz -2 0.5 MHz -24 3.5 MHz to to to to 12 16 12 24 MHz; VCC MHz; VCC MHz; VCC MHz; VCC e e e e -1 X X X X -2 X X X X -24 X X X X X X X X 5V 5V 5V 5V g 20% g 20% g 20% g 20% 272335 ±1 Figure 1. 87C51/BH Block Diagram 2 Free Datasheet http://www.datasheet4u.com/ 87C51/80C51BH/80C31BH PROCESS INFORMATION The 87C51-B H is manufactured on the CHMOS III-E process. Additional process and reliability information is available in the Intel® Quality System Handbook . PACKAGES Part 87C51-BH Package Type 40-Pin Plastic DIP (OTP) 40-Pin CERDIP (EPROM) 44-Pin PLCC (OTP) 44-Pin QFP (OTP) 272335 – 3 272335 – 2 PLCC DIP 272335 – 4 *Do not connect reserved pins. QFP Figure 2. Pin Connections 3 Free Datasheet http://www.datasheet4u.com/ 87C51/80C51BH/80C31BH Port 2 also receives some control signals and the high-order address bits during EPROM programming and program verification. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can drive LS TTL inputs. Port 3 pins that have 1's written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current (IIL, on the data sheet) because of the pullups. Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below: Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Name RXD TXD INT0 INT1 T0 T1 WR RD Alternate Function Serial input line Serial output line External Interrupt 0 External Interrupt 1 Timer 0 external input Timer 1 external input External Data Memory Write strobe External Data Memory Read strobe PIN DESCRIPTION VCC: Supply voltage during normal, Idle and Power Down operations. VSS: Circuit ground. Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink several LS TTL inputs. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this appli.


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