SN74LS114A FLIP-FLOP Datasheet

SN74LS114A Datasheet, PDF, Equivalent


Part Number

SN74LS114A

Description

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Manufacture

Motorola

Total Page 4 Pages
Datasheet
Download SN74LS114A Datasheet


SN74LS114A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS114A offers common clock and common clear inputs and
individual J, K, and set inputs. These monolithic dual flip-flops are designed
so that when the clock goes HIGH, the inputs are enabled and data will be
accepted. The logic level of the J and K inputs may be allowed to change when
the clock pulse is HIGH and the bistable will perform according to the truth
table as long as minimum set-up times are observed. Input data is transferred
to the outputs on the negative-going edge of the clock pulse.
SN54/74LS114A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
Q
6(8)
14
1
J SUFFIX
CERAMIC
CASE 632-08
CLEAR (C D )
TO
OTHER
FLIPĆFLOP
J
3(11)
13
CLOCK (CP)
MODE SELECT — TRUTH TABLE
OPERATING MODE
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
INPUTS
SD CD
LH
HL
LL
HH
HH
HH
HH
J
X
X
X
h
l
h
l
OUTPUTS
KQQ
XHL
XLH
XHH
hqq
h LH
l HL
l qq
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
4(10)
SET (S D )
K
2(12)
14
1
N SUFFIX
PLASTIC
CASE 646-06
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
4 10
3
13
SD
JQ
CP
2 K CD Q
11 S D
5J
Q
CP
12
6
K
Q
CD
9
8
1
V CC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-193
Free Datasheet http://www.datasheet4u.com/

SN74LS114A
SN54 / 74LS114A
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH Output Current — High
IOL Output Current — Low
Min Typ Max Unit
54 4.5 5.0 5.5
74 4.75 5.0 5.25
V
54 – 55 25 125 °C
74 0 25 70
54, 74
– 0.4
mA
54 4.0 mA
74 8.0
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
VIK
VOH
VOL
IIH
IIL
Input LOW Voltage
54
74
0.7 Guaranteed Input LOW Voltage for
0.8 V All Inputs
Input Clamp Diode Voltage
– 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
Output HIGH Voltage
54 2.5 3.5
74 2.7 3.5
V VCC = MIN, IOH = MAX, VIN = VIH
V or VIL per Truth Table
Output LOW Voltage
54, 74
74
0.25 0.4
0.35 0.5
V IOL = 4.0 mA VCC = VCC MIN,
VIN = VIL or VIH
V IOL = 8.0 mA per Truth Table
Input HIGH Current
J, K
Set
Clear
Clock
J, K
Set
Clear
Clock
20
60
120
µA VCC = MAX, VIN = 2.7 V
160
0.1
0.3
0.6
mA VCC = MAX, VIN = 7.0 V
0.8
Input LOW Current
J, K
Set
Clear, Clock
– 0.4
– 0.8 mA VCC = MAX, VIN = 0.4 V
– 1.6
IOS Output Short Circuit Current (Note 1) – 20
– 100 mA VCC = MAX
ICC Power Supply Current
6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
Maximum Clock Frequency
30 45
tPLH
tPHL
Propagation Delay, Clock,
Clear, Set to Output
15 20
15 20
Unit
MHz
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
tW
ts
th
Parameter
Clock Pulse Width High
Clear, Set Pulse Width
Setup Time
Hold Time
Min
20
25
20
0
Limits
Typ
Max
Unit
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
FAST AND LS TTL DATA
5-194
Free Datasheet http://www.datasheet4u.com/


Features SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIG GERED FLIP-FLOP The SN54/ 74LS114A offe rs common clock and common clear inputs and individual J, K, and set inputs. T hese monolithic dual flip-flops are des igned so that when the clock goes HIGH, the inputs are enabled and data will b e accepted. The logic level of the J an d K inputs may be allowed to change whe n the clock pulse is HIGH and the bista ble will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going e dge of the clock pulse. DUAL JK NEGATI VE EDGE-TRIGGERED FLIP-FLOP LOW POWER S CHOTTKY LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX CERAMIC CASE 632-08 14 Q 5(9) 6(8) Q 1 CLEAR (C TO OTHER FLIPĆFLO P J D ) 4(10) SET (S D ) K 2(12) 3( 11) 14 1 N SUFFIX PLASTIC CASE 646-06 13 CLOCK (CP) 14 1 D SUFFIX SOIC CA SE 751A-02 ORDERING INFORMATION MODE S ELECT — TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Lo.
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