DatasheetsPDF.com

Protection Diode. SZESD7002 Datasheet

DatasheetsPDF.com

Protection Diode. SZESD7002 Datasheet






SZESD7002 Diode. Datasheet pdf. Equivalent




SZESD7002 Diode. Datasheet pdf. Equivalent





Part

SZESD7002

Description

Low Capacitance ESD Protection Diode

Manufacture

ON Semiconductor

Datasheet
Download SZESD7002 Datasheet


ON Semiconductor SZESD7002

SZESD7002; ESD7002, SZESD7002 Transient Voltage Sup pressors Low Capacitance ESD Protection Diode for High Speed Data Line The ESD 7002 transient voltage suppressor is de signed to protect high speed data lines from ESD. Ultra−low capacitance and low ESD clamping voltage make this devi ce an ideal solution for protecting vol tage sensitive high speed data lines. T he flow−through styl.


ON Semiconductor SZESD7002

e package allows for easy PCB layout and matched trace lengths necessary to mai ntain consistent impedance between high speed differential lines such as USB 3 .0 and HDMI. Features http://onsemi.com MARKING DIAGRAM SC−70 CASE 419 STYLE 4 1 72 = Specific Device Code M = Date Code G = Pb−Free Package (*Note: Mic rodot may be in either location) 72 MG G • • • • • • • • • •.


ON Semiconductor SZESD7002

• Low Capacitance (0.3 pF Typical, I /O to GND) Diode capacitance matching P rotection for the Following IEC Standar ds: IEC 61000−4−2 (Level 4) Low ESD Clamping Voltage SZ Prefix for Automot ive and Other Applications Requiring Un ique Site and Control Change Requiremen ts; AEC−Q101 Qualified and PPAP Capab le These Devices are Pb−Free and are RoHS Compliant USB2.0/3.0 LV.



Part

SZESD7002

Description

Low Capacitance ESD Protection Diode

Manufacture

ON Semiconductor

Datasheet
Download SZESD7002 Datasheet




 SZESD7002
ESD7002, SZESD7002
Transient Voltage
Suppressors
Low Capacitance ESD Protection Diode
for High Speed Data Line
The ESD7002 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultralow capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The flowthrough style
package allows for easy PCB layout and matched trace lengths
necessary to maintain consistent impedance between high speed
differential lines such as USB 3.0 and HDMI.
Features
Low Capacitance (0.3 pF Typical, I/O to GND)
Diode capacitance matching
Protection for the Following IEC Standards:
IEC 6100042 (Level 4)
Low ESD Clamping Voltage
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AECQ101 Qualified and
PPAP Capable
These Devices are PbFree and are RoHS Compliant
Typical Applications
USB2.0/3.0
LVDS
HDMI
High Speed Differential Pairs
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range TJ 55 to +125 °C
Storage Temperature Range
Tstg 55 to +150 °C
Lead Solder Temperature
Maximum (10 Seconds)
TL 260 °C
IEC 6100042 Contact (ESD)
IEC 6100042 Air (ESD)
ESD
ESD
±8 kV
±15 kV
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
http://onsemi.com
MARKING
DIAGRAM
SC70
CASE 419
STYLE 4
72 MG
G
1
72 = Specific Device Code
M = Date Code
G = PbFree Package
(*Note: Microdot may be in either location)
PIN CONFIGURATION
AND SCHEMATIC
Pin 1 Pin 2
Pin 3
=
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
January, 2014 Rev. 3
1
Publication Order Number:
ESD7002/D
Free Datasheet http://www.datasheet4u.com/





 SZESD7002
ESD7002, SZESD7002
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Symbol
Conditions
Min Typ Max
Reverse Working
Voltage
VRWM
I/O Pin to GND
5 16
Breakdown Voltage
Reverse Leakage
Current
VBR
IR
IT = 1 mA, I/O Pin to GND
VRWM = 5 V, I/O Pin to GND
16.5
1
Clamping Voltage
(Note 1)
VC
IEC6100042, ±8 kV Contact
See Figures 3 and 4
Clamping Voltage TLP
(Note 2)
Junction Capacitance
Match
VC IPP = 8 A
IPP = 16 A
IPP = 8 A
IPP = 16 A
DCJ VR = 0 V, f = 1 MHz between I/O1 to GND and I/O
2 to GND
31.2
33.9
5.5
10.8
5
10
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins
0.2
Junction Capacitance
CJ VR = 0 V, f = 1 MHz between I/O Pins and GND
0.3
3dB Bandwidth
fBW
RL = 50 W
5
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
0.4
0.5
Unit
V
V
mA
V
%
pF
pF
GHz
1E02
1E03
1E04
1E05
1E06
1E07
1E08
1E09
1E10
1E11
1E12
1E13
0
2 4 6 8 10 12 14 16 18 20 22 24
VOLTAGE (V)
Figure 1. Typical IV Characteristic Curve
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
2 4 6 8 10 12 14
VBias (V)
Figure 2. Typical CV Characteristic Curve
150 10
140 0
130 10
120 20
110 30
100 40
90 50
80 60
70 70
60 80
50 90
40 100
30 110
20 120
10 130
0 140
10 150
50 0 50 100 150 200 250 300 350 400
20 0 20 40 60 80 100 120 140 160 180 200
TIME (ns)
Figure 3. IEC6100042 +8 kV Contact ESD
TIME (ns)
Figure 4. IEC6100042 8 kV Contact ESD
Clamping Voltage
Clamping Voltage
http://onsemi.com
2
Free
Datashe





 SZESD7002
ESD7002, SZESD7002
IEC 6100042 Spec.
Level
Test
Voltage
(kV)
First Peak
Current Current at
(A) 30 ns (A)
1 2 7.5 4
2 4 15 8
3 6 22.5 12
48
30 16
Current at
60 ns (A)
2
4
6
8
IEC6100042 Waveform
Ipeak
100%
90%
I @ 30 ns
I @ 60 ns
ESD Gun
10%
TVS
Figure 5. IEC6100042 Spec
Oscilloscope
tP = 0.7 ns to 1 ns
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D Interpretation of Datasheet Parameters
for ESD Devices.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC6100042 waveform. Since the
IEC6100042 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
http://onsemi.com
3
Free Datasheet http://www.datasheet4u.com/



Recommended third-party SZESD7002 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)