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V ADC. AD9249 Datasheet

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V ADC. AD9249 Datasheet






AD9249 ADC. Datasheet pdf. Equivalent




AD9249 ADC. Datasheet pdf. Equivalent





Part

AD9249

Description

1.8 V ADC



Feature


16 Channel, 14-Bit, 65 MSPS, Serial LVDS , 1.8 V ADC Data Sheet FEATURES Low pow er 16 ADC channels integrated into 1 pa ckage 58 mW per channel at 65 MSPS with scalable power options 35 mW per chann el at 20 MSPS SNR: 75 dBFS (to Nyquist) ; SFDR: 90 dBc (to Nyquist) DNL: ±0.6 LSB (typical); INL: ±0.9 LSB (typical) Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB.
Manufacture

Analog Devices

Datasheet
Download AD9249 Datasheet


Analog Devices AD9249

AD9249; typical Serial LVDS (ANSI-644, default) Low power, reduced signal option (simi lar to IEEE 1596.3) Data and frame cloc k outputs 650 MHz full power analog ban dwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Flexible bit orientation Built in and c ustom digital test pattern generation P rogrammable clock and data alignment Po wer-down and stand.


Analog Devices AD9249

by modes AVDD PDWN DRVDD AD9249 SIMPLIF IED FUNCTIONAL BLOCK DIAGRAM AD9249 VIN +A1 VIN–A1 VIN+A2 VIN–A2 14 ADC SER IAL LVDS 14 ADC SERIAL LVDS D+A1 D–A1 D+A2 D–A2 VIN+H1 VIN–H1 VIN+H2 VI N–H2 VREF SENSE VCM1, VCM2 SYNC 14 A DC SERIAL LVDS 14 ADC SERIAL LVDS D+H 1 D–H1 D+H2 D–H2 1.0V REF SELECT S ERIAL PORT INTERFACE DATA RATE MULTIPLI ER FCO+1, FCO+2 FCO–1, FCO–2 DCO+.


Analog Devices AD9249

1, DCO+2 DCO–1, DCO–2 11536-200 Free Datasheet http://www.datasheet4u.com/ RBIAS1, RBIAS2 GND CSB1, SDIO/ SCLK/ CSB2 DFS DTP CLK+ CLK– Figure 1. A PPLICATIONS Medical imaging Communicati ons receivers Multichannel data acquisi tion GENERAL DESCRIPTION The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-t o-digital converter (ADC) with an on-ch ip sample-and-hold circu.

Part

AD9249

Description

1.8 V ADC



Feature


16 Channel, 14-Bit, 65 MSPS, Serial LVDS , 1.8 V ADC Data Sheet FEATURES Low pow er 16 ADC channels integrated into 1 pa ckage 58 mW per channel at 65 MSPS with scalable power options 35 mW per chann el at 20 MSPS SNR: 75 dBFS (to Nyquist) ; SFDR: 90 dBc (to Nyquist) DNL: ±0.6 LSB (typical); INL: ±0.9 LSB (typical) Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB.
Manufacture

Analog Devices

Datasheet
Download AD9249 Datasheet




 AD9249
Data Sheet
FEATURES
Low power
16 ADC channels integrated into 1 package
58 mW per channel at 65 MSPS with scalable power options
35 mW per channel at 20 MSPS
SNR: 75 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist)
DNL: ±0.6 LSB (typical); INL: ±0.9 LSB (typical)
Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB
typical
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
650 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Flexible bit orientation
Built in and custom digital test pattern generation
Programmable clock and data alignment
Power-down and standby modes
APPLICATIONS
Medical imaging
Communications receivers
Multichannel data acquisition
GENERAL DESCRIPTION
The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low power
in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The AD9249 automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. Data clock outputs (DCO±1,
DCO±2) for capturing data on the output and frame clock outputs
(FCO±1, FCO±2) for signaling a new output byte are provided.
Individual channel power-down is supported, and the device
typically consumes less than 2 mW when all channels are disabled.
16 Channel, 14-Bit,
65 MSPS, Serial LVDS, 1.8 V ADC
AD9249
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN DRVDD
VIN+A1
VIN–A1
VIN+A2
VIN–A2
ADC
14
SERIAL
LVDS
AD9249
ADC
14
SERIAL
LVDS
D+A1
D–A1
D+A2
D–A2
VIN+H1
VIN–H1
VIN+H2
VIN–H2
ADC
14
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VREF
SENSE
VCM1, VCM2
SYNC
REF
SELECT
1.0V
SERIAL PORT
INTERFACE
DATA
RATE
MULTIPLIER
RBIAS1,
RBIAS2
GND CSB1, SDIO/ SCLK/
CSB2 DFS DTP
Figure 1.
CLK+ CLK–
D+H1
D–H1
D+H2
D–H2
FCO+1, FCO+2
FCO–1, FCO–2
DCO+1, DCO+2
DCO–1, DCO–2
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation.
The available digital test patterns include built-in deterministic
and pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9249 is available in an RoHS-compliant, 144-ball CSP-
BGA. It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Small Footprint. Sixteen ADCs are contained in a small,
10 mm × 10 mm package.
2. Low Power. 35 mW/channel at 20 MSPS with scalable power
options.
3. Ease of Use. Data clock outputs (DCO±1, DCO±2) operate
at frequencies of up to 455 MHz and support double data
rate (DDR) operation.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/




 AD9249
AD9249
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Simplified Functional Block Diagram ........................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Analog Input Considerations.................................................... 17
Voltage Reference ....................................................................... 18
Clock Input Considerations ...................................................... 19
Power Dissipation and Power-Down Mode ........................... 21
REVISION HISTORY
10/13—Revision 0: Initial Version
Data Sheet
Digital Outputs and Timing ..................................................... 21
Built-In Output Test Modes .......................................................... 25
Output Test Modes..................................................................... 25
Serial Port Interface (SPI).............................................................. 26
Configuration Using the SPI..................................................... 26
Hardware Interface..................................................................... 27
Configuration Without the SPI ................................................ 27
SPI Accessible Features.............................................................. 27
Memory Map .................................................................................. 28
Reading the Memory Map Register Table............................... 28
Memory Map Register Table..................................................... 29
Memory Map Register Descriptions........................................ 32
Applications Information .............................................................. 34
Design Guidelines ...................................................................... 34
Power and Ground Recommendations ................................... 34
Board Layout Considerations ................................................... 34
Clock Stability Considerations ................................................. 35
VCM............................................................................................. 35
Reference Decoupling................................................................ 35
SPI Port ........................................................................................ 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
Rev. 0 | Page 2 of 36
Free Datasheet http://www.datasheet4u.com/




 AD9249
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN DRVDD
VIN+A1
VIN–A1
VIN+A2
VIN–A2
14
ADC
SERIAL
LVDS
AD9249
ADC
14
SERIAL
LVDS
VIN+B1
VIN–B1
VIN+B2
VIN–B2
14
ADC
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VIN+C1
VIN–C1
VIN+C2
VIN–C2
14
ADC
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VIN+D1
VIN–D1
VIN+D2
VIN–D2
14
ADC
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VIN+E1
VIN–E1
VIN+E2
VIN–E2
14
ADC
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VIN+F1
VIN–F1
VIN+F2
VIN–F2
14
ADC
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VIN+G1
VIN–G1
VIN+G2
VIN–G2
14
ADC
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VIN+H1
VIN–H1
VIN+H2
VIN–H2
14
ADC
SERIAL
LVDS
ADC
14
SERIAL
LVDS
VREF
SENSE
VCM1, VCM2
SYNC
REF
SELECT
1.0V
SERIAL PORT
INTERFACE
DATA
RATE
MULTIPLIER
RBIAS1,
RBIAS2
GND CSB1, SDIO/ SCLK/
CSB2 DFS DTP
Figure 2.
CLK+ CLK–
D+A1
D–A1
D+A2
D–A2
D+B1
D–B1
D+B2
D–B2
D+C1
D–C1
D+C2
D–C2
D+D1
D–D1
D+D2
D–D2
D+E1
D–E1
D+E2
D–E2
D+F1
D–F1
D+F2
D–F2
D+G1
D–G1
D+G2
D–G2
D+H1
D–H1
D+H2
D–H2
FCO+1, FCO+2
FCO–1, FCO–2
DCO+1, DCO+2
DCO–1, DCO–2
AD9249
Rev. 0 | Page 3 of 36
Free Datasheet http://www.datasheet4u.com/






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