DatasheetsPDF.com

Agile Transceiver. AD9361 Datasheet

DatasheetsPDF.com

Agile Transceiver. AD9361 Datasheet






AD9361 Transceiver. Datasheet pdf. Equivalent




AD9361 Transceiver. Datasheet pdf. Equivalent





Part

AD9361

Description

RF Agile Transceiver



Feature


Data Sheet FEATURES RF 2 × 2 transceive r with integrated 12-bit DACs and ADCs Band: 70 MHz to 6.0 GHz Supports TDD an d FDD operation Tunable channel bandwid th: <200 kHz to 56 MHz Dual receivers: 6 differential or 12 single-ended input s Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz local o scillator (LO) RX gain control Real-tim e monitor and contr.
Manufacture

Analog Devices

Datasheet
Download AD9361 Datasheet


Analog Devices AD9361

AD9361; ol signals for manual gain Independent a utomatic gain control Dual transmitters : 4 differential outputs Highly linear broadband transmitter TX EVM: ≤−40 dB TX noise: ≤−157 dBm/Hz noise flo or TX monitor: ≥66 dB dynamic range w ith 1 dB accuracy Integrated fractional -N synthesizers 2.4 Hz maximum LO step size Multichip synchronization CMOS/LVD S digital interface RX1B_P, .


Analog Devices AD9361

RX1B_N RX1A_P, RX1A_N RX1C_P, RX1C_N RX2 B_P, RX2B_N RF Agile Transceiver AD936 1 FUNCTIONAL BLOCK DIAGRAM AD9361 ADC ADC RX LO TX LO DAC RX2C_P, RX2C_N TX_ MON1 TX1A_P, TX1A_N TX1B_P, TX1B_N TX_M ON2 TX2A_P, TX2A_N ADC DATA INTERFACE RX2A_P, RX2A_N P0_[D11:D0]/ TX_[D5:D0 ] P1_[D11:D0]/ RX_[D5:D0] DAC DAC DAC TX2B_P, TX2B_N SPI CTRL CTRL GPO PLLs RADIO SWITCHING .


Analog Devices AD9361

CLK_OUT AUXADC AUXDACx XTALP XTALN 1045 3-001 Free Datasheet http://www.datashe et4u.com/ APPLICATIONS Point to point communication systems Femtocell/picocel l/microcell base stations General-purpo se radio systems NOTES 1. SPI, CTRL, P 0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[ D5:D0], AND RADIO SWITCHING CONTAIN MUL TIPLE PINS. Figure 1. GENERAL DESCRIP TION The AD9361 is.

Part

AD9361

Description

RF Agile Transceiver



Feature


Data Sheet FEATURES RF 2 × 2 transceive r with integrated 12-bit DACs and ADCs Band: 70 MHz to 6.0 GHz Supports TDD an d FDD operation Tunable channel bandwid th: <200 kHz to 56 MHz Dual receivers: 6 differential or 12 single-ended input s Superior receiver sensitivity with a noise figure of 2 dB at 800 MHz local o scillator (LO) RX gain control Real-tim e monitor and contr.
Manufacture

Analog Devices

Datasheet
Download AD9361 Datasheet




 AD9361
Data Sheet
FEATURES
RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
TX band: 47 MHz to 6.0 GHz
RX band: 70 MHz to 6.0 GHz
Supports TDD and FDD operation
Tunable channel bandwidth: <200 kHz to 56 MHz
Dual receivers: 6 differential or 12 single-ended inputs
Superior receiver sensitivity with a noise figure of 2 dB at
800 MHz LO
RX gain control
Real-time monitor and control signals for manual gain
Independent automatic gain control
Dual transmitters: 4 differential outputs
Highly linear broadband transmitter
TX EVM: ≤−40 dB
TX noise: ≤−157 dBm/Hz noise floor
TX monitor: ≥66 dB dynamic range with 1 dB accuracy
Integrated fractional-N synthesizers
2.4 Hz maximum local oscillator (LO) step size
Multichip synchronization
CMOS/LVDS digital interface
APPLICATIONS
Point to point communication systems
Femtocell/picocell/microcell base stations
General-purpose radio systems
GENERAL DESCRIPTION
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiver™ designed for use in 3G and
4G base station applications. Its programmability and wideband
capability make it ideal for a broad range of transceiver applications.
The device combines a RF front end with a flexible mixed-signal
baseband section and integrated frequency synthesizers, simplifying
design-in by providing a configurable digital interface to a
processor. The AD9361 receiver LO operates from 70 MHz to
6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz
range, covering most licensed and unlicensed bands. Channel
bandwidths from less than 200 kHz to 56 MHz are supported.
The two independent direct conversion receivers have state-of-the-
art noise figure and linearity. Each receive (RX) subsystem includes
independent automatic gain control (AGC), dc offset correction,
quadrature correction, and digital filtering, thereby eliminating
the need for these functions in the digital baseband. The AD9361
also has flexible manual gain modes that can be externally
controlled. Two high dynamic range analog-to-digital converters
(ADCs) per channel digitize the received I and Q signals and pass
them through configurable decimation filters and 128-tap finite
Rev. F
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
RF Agile Transceiver
AD9361
FUNCTIONAL BLOCK DIAGRAM
RX1B_P,
RX1B_N
RX1A_P,
RX1A_N
RX1C_P,
RX1C_N
RX2B_P,
RX2B_N
RX2A_P,
RX2A_N
RX2C_P,
RX2C_N
TX_MON1
TX1A_P,
TX1A_N
TX1B_P,
TX1B_N
TX_MON2
TX2A_P,
TX2A_N
TX2B_P,
TX2B_N
SPI
CTRL
AD9361
ADC
RX LO
TX LO
ADC
DAC
CTRL
DAC
GPO
PLLs
P0_[D11:D0]/
TX_[D5:D0]
P1_[D11:D0]/
RX_[D5:D0]
RADIO
SWITCHING
CLK_OUT
AUXADC AUXDACx XTALP XTALN
NOTES
1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],
AND RADIO SWITCHING CONTAIN MULTIPLE PINS.
Figure 1.
impulse response (FIR) filters to produce a 12-bit output signal at
the appropriate sample rate.
The transmitters use a direct conversion architecture that achieves
high modulation accuracy with ultralow noise. This transmitter
design produces a best in class TX error vector magnitude (EVM)
of <−40 dB, allowing significant system margin for the external
power amplifier (PA) selection. The on-board transmit (TX)
power monitor can be used as a power detector, enabling highly
accurate TX power measurements.
The fully integrated phase-locked loops (PLLs) provide low
power fractional-N frequency synthesis for all receive and
transmit channels. Channel isolation, demanded by frequency
division duplex (FDD) systems, is integrated into the design.
All VCO and loop filter components are integrated.
The core of the AD9361 can be powered directly from a 1.3 V
regulator. The IC is controlled via a standard 4-wire serial port
and four real-time input/output control pins. Comprehensive
power-down modes are included to minimize power consumption
during normal use. The AD9361 is packaged in a 10 mm × 10 mm,
144-ball chip scale package ball grid array (CSP_BGA).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




 AD9361
AD9361
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Current Consumption—VDD_Interface .................................. 8
Current Consumption—VDDD1P3_DIG and VDDAx
(Combination of all 1.3 V Supplies)......................................... 10
Absolute Maximum Ratings ..................................................... 15
Reflow Profile.............................................................................. 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 20
800 MHz Frequency Band......................................................... 20
2.4 GHz Frequency Band .......................................................... 25
5.5 GHz Frequency Band .......................................................... 29
REVISION HISTORY
11/2016—Rev. E to Rev. F
Changes to Features Section and General Description Section . 1
Change to Transmitter—General, Center Frequency Parameter,
Minimum Column, Table 1............................................................. 4
11/2014—Rev. D to Rev. E
Changes to Table 1............................................................................ 7
Data Sheet
Theory of Operation ...................................................................... 33
General......................................................................................... 33
Receiver........................................................................................ 33
Transmitter.................................................................................. 33
Clock Input Options .................................................................. 33
Synthesizers................................................................................. 34
Digital Data Interface................................................................. 34
Enable State Machine................................................................. 34
SPI Interface ................................................................................ 35
Control Pins ................................................................................ 35
GPO Pins (GPO_3 to GPO_0) ................................................. 35
Auxiliary Converters.................................................................. 35
Powering the AD9361................................................................ 35
Packaging and Ordering Information ......................................... 36
Outline Dimensions................................................................... 36
Ordering Guide .......................................................................... 36
11/2013—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 36
9/2013—Revision C: Initial Version
Rev. F | Page 2 of 36




 AD9361
Data Sheet
AD9361
SPECIFICATIONS
Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter1
RECEIVERS, GENERAL
Center Frequency
Gain
Minimum
Maximum
Symbol Min
70
Gain Step
Received Signal Strength
Indicator
Range
Accuracy
RECEIVERS, 800 MHz
Noise Figure
Third-Order Input Intermodulation
Intercept Point
Second-Order Input
Intermodulation Intercept Point
Local Oscillator (LO) Leakage
Quadrature
Gain Error
Phase Error
Modulation Accuracy (EVM)
Input S11
RX1 to RX2 Isolation
RX1A to RX2A, RX1C to RX2C
RX1B to RX2B
RX2 to RX1 Isolation
RX2A to RX1A, RX2C to RX1C
RX2B to RX1B
RECEIVERS, 2.4 GHz
Noise Figure
Third-Order Input Intermodulation
Intercept Point
Second-Order Input
Intermodulation Intercept Point
LO Leakage
RSSI
NF
IIP3
IIP2
NF
IIP3
IIP2
Quadrature
Gain Error
Phase Error
Modulation Accuracy (EVM)
Input S11
RX1 to RX2 Isolation
RX1A to RX2A, RX1C to RX2C
RX1B to RX2B
RX2 to RX1 Isolation
RX2A to RX1A, RX2C to RX1C
RX2B to RX1B
Typ
0
74.5
73.0
72.0
65.5
1
100
±2
2
−18
40
−122
0.2
0.2
−42
−10
70
55
70
55
3
−14
45
−110
0.2
0.2
−42
−10
65
50
65
50
Max
6000
Test Conditions/
Unit Comments
MHz
dB
dB At 800 MHz
dB At 2300 MHz (RX1A, RX2A)
dB At 2300 MHz (RX1B,
RX1C, RX2B, RX2C)
dB At 5500 MHz (RX1A, RX2A)
dB
dB
dB
dB Maximum RX gain
dBm Maximum RX gain
dBm Maximum RX gain
dBm At RX front-end input
%
Degrees
dB
dB
19.2 MHz reference clock
dB
dB
dB
dB
dB Maximum RX gain
dBm Maximum RX gain
dBm Maximum RX gain
dBm At receiver front-end
input
%
Degrees
dB
dB
40 MHz reference clock
dB
dB
dB
dB
Rev. F | Page 3 of 36






Recommended third-party AD9361 Datasheet






@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)