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DDR SDRAM. A3S12D40ETP Datasheet

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DDR SDRAM. A3S12D40ETP Datasheet






A3S12D40ETP SDRAM. Datasheet pdf. Equivalent




A3S12D40ETP SDRAM. Datasheet pdf. Equivalent





Part

A3S12D40ETP

Description

(A3S12D30ETP / A3S12D40ETP) 512Mb DDR SDRAM



Feature


512Mb DDR SDRAM Specification A3S12D30ET P A3S12D40ETP Powerchip Semiconductor Corp. No.12 Li-Hsin Rd.1,Science-based Industrial Park ,Hsin-Chu Taiwan, R.O.C . TEL:886-3-5795000 FAX:886-3-5792168 Free Datasheet http://www.datasheet4u.n et/ Powerchip Semiconductor Corporatio n A3S12D30/40ETP 512Mb DDR Synchronous DRAM PRELIMINARY Some of contents are subject to change .
Manufacture

Powerchip

Datasheet
Download A3S12D40ETP Datasheet


Powerchip A3S12D40ETP

A3S12D40ETP; without notice. DESCRIPTION A3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit, A3S12D40ETP is a 4-bank x 8,388,608-wo rd x 16-bit, double data rate synchrono us DRAM, with SSTL_2 interface. All con trol and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data str obe, and output data and data strobe ar e referenced on bo.


Powerchip A3S12D40ETP

th edges of CLK. The A3S12D30/40ETP achi eves very high speed data rate up to 20 0MHz, and are suitable for main memory in computer systems. FEATURES - Vdd=Vd dq=2.5V+0.2V (for speed grade -6, 7.5) - Vdd=Vddq=2.6V+0.1V (for speed grade - 5) - Double data rate architecture; two data transfers per clock cycle - Bidir ectional, data strobe (DQS) is transmit ted/received with .


Powerchip A3S12D40ETP

data - Differential clock inputs (CLK an d /CLK) - DLL aligns DQ and DQS transit ions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - Four internal ba nks for concurrent opertation - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5/3.0 (p rogrammable) - Bur.

Part

A3S12D40ETP

Description

(A3S12D30ETP / A3S12D40ETP) 512Mb DDR SDRAM



Feature


512Mb DDR SDRAM Specification A3S12D30ET P A3S12D40ETP Powerchip Semiconductor Corp. No.12 Li-Hsin Rd.1,Science-based Industrial Park ,Hsin-Chu Taiwan, R.O.C . TEL:886-3-5795000 FAX:886-3-5792168 Free Datasheet http://www.datasheet4u.n et/ Powerchip Semiconductor Corporatio n A3S12D30/40ETP 512Mb DDR Synchronous DRAM PRELIMINARY Some of contents are subject to change .
Manufacture

Powerchip

Datasheet
Download A3S12D40ETP Datasheet




 A3S12D40ETP
512Mb DDR SDRAM Specification
A3S12D30ETP
A3S12D40ETP
Powerchip Semiconductor Corp.
No.12 Li-Hsin Rd.1,Science-based Industrial Park ,Hsin-Chu
Taiwan, R.O.C.
TEL:886-3-5795000
FAX:886-3-5792168
Free Datasheet http://www.datasheet4u.net/




 A3S12D40ETP
Powerchip Semiconductor Corporation
A3S12D30/40ETP
512Mb DDR Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
A3S12D30ETP is a 4-bank x 16,777,216-word x 8-bit,
A3S12D40ETP is a 4-bank x 8,388,608-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The A3S12D30/40ETP achieves very
high speed data rate up to 200MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V (for speed grade -6, 7.5)
- Vdd=Vddq=2.6V+0.1V (for speed grade -5)
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- Four internal banks for concurrent opertation
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5/3.0 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-12 / Column address A0-9,11,12(x4)/ A0-9,11(x8)/ A0-9(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- JEDEC standard
Operating Frequencies
Speed
Grade
-5
CL=2.0 *
133MHz
Clock Rate
CL=2.5 *
167MHz
CL=3.0 *
200MHz
-6 133MHz 167MHz 167MHz
-75 100MHz 133MHz 133MHz
* CL = CAS(Read) Latency
Free Datasheet http://www.datasheet4u.net/




 A3S12D40ETP
Powerchip Semiconductor Corporation
A3S12D30/40ETP
512Mb DDR Synchronous DRAM
PIN CONFIGURATION(TOP VIEW)
x8
x16
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66pin TSOP(II)
400mil width
x
875mil length
0.65mm
Lead Pitch
ROW
A0-12
Column
A0-9,11 (x8)
A0-9 (x16)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
CLK, /CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-3
DQ0-7
DQ0-15
DQS
UDQS, LDQS
DM
UDM, LDM
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O (x4)
: Data I/O (x8)
: Data I/O (x16)
: Data Strobe (x4/x8)
: Data Strobe (x16)
: Write Mask (x4/x8)
: Write Mask (x16)
A0-12
BA0,1
Vdd
VddQ
Vss
VssQ
Vref
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
: Reference Voltage
Free Datasheet http://www.datasheet4u.net/






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