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PC28F512G18FE Dataheets PDF



Part Number PC28F512G18FE
Manufacturers Micron
Logo Micron
Description StrataFlash Embedded Memory
Datasheet PC28F512G18FE DatasheetPC28F512G18FE Datasheet (PDF)

128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Micron StrataFlash Embedded Memory P/N P/N P/N P/N – – – – PC28F128G18xx PC28F256G18xx PC28F512G18xx PC28F00AG18xx • Power – Core voltage: 1.7 V - 2.0 V – I/O voltage: 1.7 V - 2.0 V – Standby current: 60 μA (typ) for 512-Mbit, 65 nm – Deep Power-Down mode: 2 μA (typ) – Automatic Power Savings mode – 16-word synchronous-burst read current: 23 mA (typ) @ 108 MHz; 24 mA (typ) @ 133 MHz • Software – Micron® Flash data integrator (FDI) optimized –.

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128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Micron StrataFlash Embedded Memory P/N P/N P/N P/N – – – – PC28F128G18xx PC28F256G18xx PC28F512G18xx PC28F00AG18xx • Power – Core voltage: 1.7 V - 2.0 V – I/O voltage: 1.7 V - 2.0 V – Standby current: 60 μA (typ) for 512-Mbit, 65 nm – Deep Power-Down mode: 2 μA (typ) – Automatic Power Savings mode – 16-word synchronous-burst read current: 23 mA (typ) @ 108 MHz; 24 mA (typ) @ 133 MHz • Software – Micron® Flash data integrator (FDI) optimized – Basic command set (BCS) and extended command set (ECS) compatible – Common Flash interface (CFI) capable • Security – One-time programmable (OTP) space 64 unique factory device identifier bits 2112 user-programmable OTP bits – Absolute write protection: V PP = GND – Power-transition erase/program lockout – Individual zero latency block locking – Individual block lock-down • Density and packaging – 128Mb, 256Mb, 512Mbit, and 1-Gbit – Address-data multiplexed and non-multiplexed interfaces – 64-Ball Easy BGA Features • High-Performance Read, Program and Erase – 96 ns initial read access – 108 MHz with zero wait-state synchronous burst reads: 7 ns clock-to-data output – 133 MHz with zero wait-state synchronous burst reads: 5.5 ns clock-to-data output – 8-, 16-, and continuous-word synchronous-burst Reads – Programmable WAIT configuration – Customer-configurable output driver impedance – Buffered Programming: 2.0 μs/Word (typ), 512Mbit 65 nm – Block Erase: 0.9 s per block (typ) – 20 μs (typ) program/erase suspend • Architecture – 16-bit wide data bus – Multi-Level Cell Technology – Symmetrically-Blocked Array Architecture – 256-Kbyte Erase Blocks – 1-Gbit device: Eight 128-Mbit partitions – 512-Mbit device: Eight 64-Mbit partitions – 256-Mbit device: Eight 32-Mbit partitions – 128-Mbit device: Eight 16-Mbit partitions – Read-While-Program and Read-While-Erase – Status Register for partition/device status – Blank Check feature • Quality and Reliability – Expanded temperature: –30 °C to +85 °C – Minimum 100,000 erase cycles per block – 65nm Process Technology PDF: 09005aef8448483a 128_256_512_65nm_g18.pdf - Rev. E 8/11 EN 1 Products and specifications discussed herein are subject to change by Micron without notice. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2011 Micron Technology, Inc. All rights reserved. Free Datasheet http://www.datasheet4u.net/ 128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory Features Contents General Description ......................................................................................................................................... 8 Functional Overview ........................................................................................................................................ 8 Configuration and Memory Map ....................................................................................................................... 9 Device ID ....................................................................................................................................................... 12 Package Dimensions ....................................................................................................................................... 13 Signal Assignments ......................................................................................................................................... 14 Signal Descriptions ......................................................................................................................................... 15 Bus Interface .................................................................................................................................................. 16 Reset .......................................................................................................................................................... 16 Standby ..................................................................................................................................................... 16 Output Disable ........................................................................................................................................... 16 Asynchronous Read .................................................................................................................................... 17 Synchronous Read ...................................................................................................................................... 17 Burst Wrapping .......................................................................................................................................... 17 End-of-Wordline Delay ............................................................................................................................... 18 Write ..................................................................................................................


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