Document
K9G8G08U0A-W000
FLASH MEMORY DIE
K9G8G08U0A
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* Samsung Electronics reserves the right to change products or specification without notice.
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Free Datasheet http://www.datasheet4u.net/
K9G8G08U0A-W000
Document Title
SAMSUNG 8Gb(1G x8 Bit) NAND FLASH A-DIE
FLASH MEMORY DIE
Revision History
Revision No
0.0
History
Initial Draft
Date
Jau. 18, 2006
Remark
Advanced
0.1
Logo lacation is marked
Feb. 9th 2007
Advanced
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Free Datasheet http://www.datasheet4u.net/
K9G8G08U0A-W000
1.0 Product Introduction
1.1 Features
• • • • • • • Power Supply Voltage : 2.7V ~ 3.6V Organization : (1G+32M) x 8bit May contain up to 100 invalid blocks Functionally Tested Only 256KB Block Erase operation 2KB Page Program/ Read Operation Tray Packing for Chip or Jar Packing for Wafer
FLASH MEMORY DIE
1.2 General Physical Specifications
• • • • Backside die surface of polished bare silicon Die Thickness = 725±10um(Bare Wafer) or 200um (Back Lap) Typical top-level metalization Single barrier metal : - 6.0K Angstroms Al - 0.2% Si + 0.5% Cu composition • Top side passivation : - 1.0K Angstroms PEOX - 7K Angstroms HDP OX - 3K Angstroms SiN - 6.5um PSPI/ 10um Polyimide • Typical Pad Size : 90.0um x 90.0um • Die Size : 7916um x 10906um including scribe line (X : 7816um Y : 10806um scribe line)
DIE OUTLINE (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
8Gb NAND FLASH A-DIE PAD Diagram
7,816um x 10,806um including X:7,916um Y:10,906um scribe line Pad Size : 90.0um x 90.0um
LOGO
X-Axis
Y-Axis
(0,0)
Wafer Flat Zone
Figure 1. Pad Diagram
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K9G8G08U0A-W000
1.3 Functional Specifications
FLASH MEMORY DIE
A bare die is tested for only DC parameters and functional items. Please refer to the packaged product data sheet for functional and parametric specifications. For bare die, these specifications are provided for reference only and SAMSUNG makes no guarantees or warranties on bare die.
1.4 Standard Probe Testing
Wafer probe consists of various functional and parametric tests of each die. Test patterns, timing, voltage margins, limits, and test sequence are determined by individual product yields and reliability data. SAMSUNG retains a wafer map of each wafer as part of the probe records along with a lot summary of wafer yields for each lot probed. SAMSUNG reserves the right to change the probe program at any time to improve the reliability, packaged device yield, or performance of the product.
1.5 Bonding Instructions
The 8Gb NAND Flash A-die has total 33pads. Refer to the bond pad location and identification table for a complete list of bond pads and X, Y coordinates. SAMSUNG recommends using a bond wire on each Vcc and Vss bond pad for improved noise immunity. Table 1. Bond Pad Location and Identification PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 FUNCTION IO0 IO1 IO2 IO3 NC NC WP WE NC ALE CLE NC NC Vss Vss NC VDD X 7596.5 7292.9 6989.3 6685.7 6230.3 6078.5 5926.7 5623.1 5471.3 5319.5 5015.9 4896.3 4776.7 4657.1 4353.5 4201.7 4049.9 Y 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 PAD 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 FUNCTION VDD NC NC NC NC CE NC RE R/B NC NC IO4 IO5 IO6 IO7 NC X 3746.3 3442.7 3139.1 3019.5 2899.9 2690.1 2538.3 2386.5 2082.9 1931.1 1779.3 1323.9 1020.3 716.7 413.1 189.6 Y 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68 118.68
NOTE: 1. Referenced to the center of each pad from the corner of left bottom. 2. All units are in um 3. NC stands for No Connection.
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K9G8G08U0A-W000
1.6 Packing
FLASH MEMORY DIE
• Tray Packing for Chip A 2-inch square waffle style carrier for die with separate compartments for each die. Each tray has a cavity size selected for the device that allows for easy loading and unloading and prevents rotation. The tray itself is made of conductive material to reduce the danger of damage to the die from electrostatic discharge. The chip carriers will be labeled with the follo.