SC2597

POWER MANAGEMENT Features „„ Input to linear regulator (VIN): 1.0V to 3.6V „„ Output (VTT): 0.5V to 1.8V „„ Bias Voltage (VDD): 2.35V to 3.6V „„ Up to 3A sink or source from VTT for DDR through DDR4 „„ + 1% over temperature (with respect to VDDQ/2, in- cluding internal resistor divider variation) VREF and VTT „„ Logic-level enable input „„ Built in soft-start „„ Thermal shutdown with auto-restart „„ Over current protection „„ Minimal output capacitance „„ Package: SOIC8-EDP Applications „„ DDR Memory Termination SC2597 Low Voltage DDR Termination Regulator Description The SC2597 is designed to meet the latest JEDEC specification for low power DDR3 and DDR4, while also supporting DDR and DDR2. The SC2597 regulates up to + 3A for VTT and up to + 40mA for VREF. The SC2597 also provides an accuracy of +1% over temperature (which takes into account the internal resistor divider) for VREF and VTT for the memory controller and DRAM. SC2597 protection features include thermal shutdown with auto-restart for VTT and over-current limit for both VTT and VREF. Under-Voltage-Lock-Out circuits are included to ensure that the output is off when the bias voltage falls below its threshold, and that the part behaves elegantly in powerup or power-down. The low external parts count combined with industry leading specifications make SC2597 an attractive solution for DDR through DDR4 termination. Typical Application Circuit CVDD 1µF CIN 2x10µF Rev. 2.9 VDDQ VDD VIN VDDQ VTT VTTS VREF EN G...