Hi3512 H.264 Encoding and Decoding Processor
Key Features
CPU Core
●ARM926EJ-S, 16 KB instruction cache, and 16 KB data ...
Hi3512 H.264 Encoding and Decoding Processor
Key Features
CPU Core
●ARM926EJ-S, 16 KB instruction cache, and 16 KB data cache ●Embedded close coupling memory with 2 KB instruction ●32-bit RISC processor with the Harvard architecture ●Built-in MMU supporting various open operating systems ●Up to 288 MHz operating frequency
Video Interfaces
●Input −2 channels of BT.656/601 YCrCb 4:2:2, 8 bits. Each interface supports two channels of BT.656 multiplex video input. SMPTE296M 720P, YC 4:2:2, 16 bits CCD and CMOS digital interfaces. ●Output −1-channel BT.656 interface.
●USB 2.0 OTG ●MII interface ,10/100Mbit/s duplex ●RTC, independent supply power
Memory Interface
●DDR2 SDRAM interface −16 bits or 32 bits −Up to 512 MB ●NOR flash interface −8 bits −2 banks, each up to 32 MB
Audio Interfaces
●I2S x 2 −8 bits, 16 bits or 32 bits −\Sample frequency of 4–48 kHz.
Video Encoding and Decoding
●H.264 Main
[email protected] encoding and decoding ●H.264 Baseline
[email protected] encoding and decoding ●MJPEG/JPEG Baseline encoding and decoding
SDK
●Linux-based SDK ●High-performance H.264 PC decoding library
Peripheral Interfaces
●PCI V2.3 −Compatible with the miniPCI −Supporting the master and slave modes ●UART x 3 ●IR ●I2C ●SPI, master and slave modes ●GPIO ●SDIO 2.0 ●USB 1.1 Host
Power Consumption
●600 mW typical power consumption ●Multiple levels of power-down modes
Operating voltage
●1.2 V for core ●3.3 V for IO with 5 V tolerance ●1.8 V for DDR2 DRAM I/O
Video Processing Performa...