71V256SA IDT71V256SA Datasheet

71V256SA Datasheet, PDF, Equivalent


Part Number

71V256SA

Description

IDT71V256SA

Manufacture

IDT

Total Page 6 Pages
Datasheet
Download 71V256SA Datasheet


71V256SA
Integrated Device Technology, Inc.
LOW POWER
3.3V CMOS FAST SRAM
256K (32K x 8-BIT)
IDT71V256SA
FEATURES
• Ideal for high-performance processor secondary cache
• Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
• Fast access times:
— Commercial: 10/12/15/20ns
— Industrial: 15ns
• Low standby current (maximum):
— 2mA full standby
• Small packages for space-efficient layouts:
— 28-pin 300 mil SOJ
— 28-pin 300 mil plastic DIP (Commercial only)
— 28-pin TSOP Type I
• Produced with advanced high-performance CMOS
technology
• Inputs and outputs are LVTTL-compatible
• Single 3.3V(±0.3V) power supply
DESCRIPTION
The IDT71V256SA is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology.
The IDT71V256SA has outstanding low power character-
istics while at the same time maintaining very high perfor-
mance. Address access times of as fast as10 ns are ideal for
3.3V secondary cache in 3.3V desktop designs.
When power management logic puts the IDT71V256SA in
standby mode, its very low power characteristics contribute to
extended battery life. By taking CS HIGH, the SRAM will
automatically go to a low power standby mode and will remain
in standby as long as CS remains HIGH. Furthermore, under
full standby mode (CS at CMOS level, f=0), power consump-
tion is guaranteed to always be less than 6.6mW and typically
will be much smaller.
The IDT71V256SA is packaged in 28-pin 300 mil SOJ, 28-
pin 300 mil plastic DIP, and 28-pin 300 mil TSOP Type I
packaging.
FUNCTIONAL BLOCK DIAGRAM
A0
ADDRESS
DECODER
A14
I/O0
INPUT
DATA
CIRCUIT
I/O7
CS
OE CONTROL
WE CIRCUIT
262,144 BIT
MEMORY ARRAY
I/O CONTROL
VCC
GND
3101 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1997 Integrated Device Technology, Inc.
MAY 1997
DSC-3101/04
1
Free Datasheet http://www.datasheet-pdf.com/

71V256SA
IDT71V256SA
3.3V CMOS STATIC RAM 256K (32K x 8-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS(1)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1 28
2 27
3 26
4 25
5 24
6 23
7 SO28-5 22
P28-2
8 21
9 20
10 19
11 18
12 17
13 16
14 15
DIP/SOJ
TOP VIEW
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
3101 drw 02
OE
A 11
A9
A8
A 13
WE
V CC
A 14
A 12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
SO28-8
TSOP
TOP VIEW
21 A 10
20 CS
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
14 GND
13 I/O2
12 I/O1
11 I/O0
10 A 0
9 A1
8 A2
3101 drw 11
Symbol
Rating
Value
Unit
VCC
VTERM(2)
Supply Voltage
Relative to GND
Terminal Voltage
Relative to GND
–0.5 to +4.6
V
–0.5 to VCC+0.5 V
TBIAS
Temperature Under Bias –55 to +125
°C
TSTG
Storage Temperature
–55 to +125
°C
PT Power Dissipation
1.0 W
IOUT
DC Output Current
50 mA
NOTES:
3101 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Input, Output, and I/O terminals; 4.6V maximum.
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter(1)
Conditions Max. Unit
CIN Input Capacitance
VIN = 3dV
6 pF
COUT Output Capacitance VOUT = 3dV
7 pF
NOTE:
3101 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
PIN DESCRIPTIONS
Name
A0–A14
I/O0–I/O7
CS
WE
OE
GND
VCC
Description
Addresses
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
Power
TRUTH TABLE(1)
3101 tbl 01
I/OWE
CS
OE
X H X High-Z
X VHC X High-Z
H L H High-Z
H L L DOUT
L LX
NOTE:
1. H = VIH, L = VIL, X = Don’t Care
DIN
Function
Standby (ISB)
Standby (ISB1)
Output Disable
Read
Write
3101 tbl 02
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Temperature
GND
VCC
Commercial
0°C to +70°C
0V 3.3V ± 0.3V
Industrial
-40°C to +85°C
0V 3.3V ± 0.3V
3101 tbl 05
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
VCC Supply Voltage
3.0 3.3 3.6 V
GND Supply Voltage
00
0V
VIH Input High Voltage - Inputs 2.0 — 5.0 V
VIH
Input High Voltage - I/O
2.0 — Vcc+0.3 V
VIL Input Low Voltage
–0.3(1)
0.8 V
NOTE:
3101 tbl 06
1. VIL (min.) = –2.0V for pulse width less than 5ns, once per cycle.
2
Free Datasheet http://www.datasheet-pdf.com/


Features LOW POWER 3.3V CMOS FAST SRAM 256K (32K x 8-BIT) Integrated Device Technology, Inc. IDT71V256SA FEATURES • Ideal f or high-performance processor secondary cache • Commercial (0° to 70°C) an d Industrial (-40° to 85°C) temperatu re options • Fast access times: — C ommercial: 10/12/15/20ns — Industrial : 15ns • Low standby current (maximum ): — 2mA full standby • Small packa ges for space-efficient layouts: — 28 -pin 300 mil SOJ — 28-pin 300 mil pla stic DIP (Commercial only) — 28-pin T SOP Type I • Produced with advanced h igh-performance CMOS technology • Inp uts and outputs are LVTTL-compatible Single 3.3V(±0.3V) power supply DES CRIPTION The IDT71V256SA is a 262,144-b it high-speed static RAM organized as 3 2K x 8. It is fabricated using IDT’s highperformance, high-reliability CMOS technology. The IDT71V256SA has outstan ding low power characteristics while at the same time maintaining very high pe rformance. Address access times of as fast as10 ns are ideal for 3.3V secondary cache in 3.3V desk.
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