NAND gate. HEF4011B Datasheet

HEF4011B gate. Datasheet pdf. Equivalent

Part HEF4011B
Description Quadruple 2-input NAND gate
Feature INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS H.
Manufacture NXP
Datasheet
Download HEF4011B Datasheet



HEF4011B
HEF4011B
Quad 2-input NAND gate
Rev. 5 — 21 November 2011
Product data sheet
1. General description
The HEF4011B is a quad 2-input NAND gate. The outputs are fully buffered for the
highest noise immunity and pattern insensitivity to output impedance.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
Inputs and outputs are protected against electrostatic effects
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C
Type number Package
Name Description
HEF4011BP DIP14 plastic dual in-line package; 14 leads (300 mil)
HEF4011BT SO14 plastic small outline package; 14 leads; body width 3.9 mm
4. Functional diagram
Version
SOT27-1
SOT108-1
1A 1
1B 2
2A 5
2B 6
3A 8
3B 9
4A 12
4B 13
3 1Y
4 2Y
10 3Y
11 4Y
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Fig 1. Functional diagram
nA
nB
nY
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Fig 2. Logic diagram (one gate)



HEF4011B
NXP Semiconductors
5. Pinning information
5.1 Pinning
Fig 3. Pin configuration
1A 1
1B 2
1Y 3
2Y 4
2A 5
2B 6
VSS 7
14 VDD
13 4B
12 4A
HEF4011B 11 4Y
10 3Y
9 3B
8 3A
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5.2 Pin description
Table 2.
Symbol
nA
nB
nY
VSS
VDD
Pin description
Pin
1, 5, 8, 12
2, 6, 9, 13
3, 4, 10, 11
7
14
Description
input
input
output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
L
H
H
Function table[1]
nB
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level.
Output
nY
H
H
H
L
HEF4011B
Quad 2-input NAND gate
HEF4011B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 November 2011
© NXP B.V. 2011. All rights reserved.
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