HEF4011UB

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4011UB gates Quadruple 2-input NAND gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple 2-input NAND gate DESCRIPTION The HEF4011UB is a quadruple 2-input NAND gate. This unbuffered single stage version provides a direct implementation of the NAND function. The output impedance and output transition time depends on the input voltage and input rise and fall times applied. HEF4011UB gates Fig.2 Pinning diagram. HEF4011UBP(N): Fig.1 Functional diagram. HEF4011UBD(F): HEF4011UBT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Schematic diagram (one gate). The splitting-up of the n-transistors provide identical inputs. FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages January 1995 2 Philips Semiconductors Product specification Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW LOW to HIGH Input capacitance 10 15 5 10 15 5 10 15 CIN tTLH tTHL tPLH tPHL 60 25 20 35 20 17 ...