NAND gate. HEF4011UB Datasheet

HEF4011UB gate. Datasheet pdf. Equivalent

Part HEF4011UB
Description Quadruple 2-input NAND gate
Feature INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS H.
Manufacture NXP
Datasheet
Download HEF4011UB Datasheet




HEF4011UB
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4011UB
gates
Quadruple 2-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995



HEF4011UB
Philips Semiconductors
Quadruple 2-input NAND gate
DESCRIPTION
The HEF4011UB is a quadruple 2-input NAND gate. This
unbuffered single stage version provides a direct
implementation of the NAND function. The output
impedance and output transition time depends on the input
voltage and input rise and fall times applied.
Product specification
HEF4011UB
gates
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4011UBP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4011UBD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4011UBT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Schematic diagram (one gate). The
splitting-up of the n-transistors provide
identical inputs.
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications for VIH/VIL unbuffered stages
January 1995
2







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