NAND gate. HEF4012B Datasheet

HEF4012B gate. Datasheet pdf. Equivalent

HEF4012B Datasheet
Recommendation HEF4012B Datasheet
Part HEF4012B
Description Dual 4-input NAND gate
Feature HEF4012B; INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS H.
Manufacture NXP
Datasheet
Download HEF4012B Datasheet




NXP HEF4012B
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4012B
gates
Dual 4-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995



NXP HEF4012B
Philips Semiconductors
Dual 4-input NAND gate
DESCRIPTION
The HEF4012B provides the positive dual 4-input NAND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Product specification
HEF4012B
gates
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
HEF4012BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4012BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4012BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
see Family Specifications
January 1995
2



NXP HEF4012B
Philips Semiconductors
Dual 4-input NAND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL
TYP
MAX
Propagation delays
In On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10
15
5
10
15
5
10
15
5
10
15
tPHL
tPLH
tTHL
tTLH
70 135
25 50
20 35
70 140
30 60
25 50
60 120
30 60
20 40
60 120
30 60
20 40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Product specification
HEF4012B
gates
TYPICAL EXTRAPOLATION
FORMULA
43 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
43 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1100 fi + ∑ (foCL) × VDD2
where
10
4400 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
12 900 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3





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