NAND gate. HEF4023B Datasheet

HEF4023B gate. Datasheet pdf. Equivalent

HEF4023B Datasheet
Recommendation HEF4023B Datasheet
Part HEF4023B
Description Triple 3-input NAND gate
Feature HEF4023B; INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS H.
Manufacture NXP
Datasheet
Download HEF4023B Datasheet




NXP HEF4023B
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4023B
gates
Triple 3-input NAND gate
Product specification
File under Integrated Circuits, IC04
January 1995



NXP HEF4023B
Philips Semiconductors
Triple 3-input NAND gate
DESCRIPTION
The HEF4023B provides the positive triple 3-input NAND
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Product specification
HEF4023B
gates
Fig.1 Functional diagram.
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
Fig.2 Pinning diagram.
HEF4023BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4023BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4023BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
January 1995
2



NXP HEF4023B
Philips Semiconductors
Triple 3-input NAND gate
Product specification
HEF4023B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL
TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10 tPLH
15
5
10 tTHL
15
5
10 tTLH
15
65 135 ns 38 ns + (0,55 ns/pF) CL
25
50 ns
14 ns + (0,23 ns/pF) CL
15 30 ns 7 ns + (0,16 ns/pF) CL
65 130 ns 38 ns + (0,55 ns/pF) CL
30
60 ns
19 ns + (0,23 ns/pF) CL
25
45 ns
17 ns + (0,16 ns/pF) CL
60 120 ns 10 ns + (1,0 ns/pF) CL
30 60 ns 9 ns + (0,42 ns/pF) CL
20 40 ns 6 ns + (0,28 ns/pF) CL
60 120 ns 10 ns + (1,0 ns/pF) CL
30 60 ns 9 ns + (0,42 ns/pF) CL
20 40 ns 6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1200 fi + ∑ (foCL) × VDD2
where
10
5500 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
16 400 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)