HEF4024B

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4024B MSI 7-stage binary counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 7-stage binary counter DESCRIPTION The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. HEF4024B MSI Fig.1 Functional diagram. PINNING CP MR O0 to O6 clock input (HIGH to LOW triggered) master reset input buffered parallel outputs APPLICATION INFORMATION Some examples of applications for the HEF4024B are: Frequency dividers Time delay circuits Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications HEF4024BP(N): HEF4024BD(F): HEF4024BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape...