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H5PS1G63JFR-xxJ Dataheets PDF



Part Number H5PS1G63JFR-xxJ
Manufacturers hynix
Logo hynix
Description 1Gb DDR2 SDRAM
Datasheet H5PS1G63JFR-xxJ DatasheetH5PS1G63JFR-xxJ Datasheet (PDF)

H5PS1G63JFR Series 1Gb DDR2 SDRAM H5PS1G63JFR-xxC H5PS1G63JFR-xxI H5PS1G63JFR-xxL H5PS1G63JFR-xxJ This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.7 / Nov. 2011 1 Free Datasheet http://www.datasheetlist.com/ Release H5PS1G63JFR Series Revision Details Rev. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 History Released Type Correction - Specifi.

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H5PS1G63JFR Series 1Gb DDR2 SDRAM H5PS1G63JFR-xxC H5PS1G63JFR-xxI H5PS1G63JFR-xxL H5PS1G63JFR-xxJ This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.7 / Nov. 2011 1 Free Datasheet http://www.datasheetlist.com/ Release H5PS1G63JFR Series Revision Details Rev. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 History Released Type Correction - Specific Notes for dedicated AC parameters 15 Update IDD Updated tREFI Condition & VREF units Updated IDD Values (3PF/3PS) PKG dimension update PKG dimension update Operating Temp & Key Features update Draft Date Mar. 2011 Aug. 2011 Aug. 2011 Sep. 2011 Sep. 2011 Nov. 2011 Nov. 2011 Nov. 2011 Rev. 1.7 / Nov. 2011 2 Free Datasheet http://www.datasheetlist.com/ Release H5PS1G63JFR Series Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Features 1.1.2 Ordering Information 1.1.3 Operating Frequency 1.2 Pin configuration 1.3 Pin Description 2. Maximum DC ratings 2.1 Absolute Maximum DC Ratings 2.2 Operating Temperature Condition 3. AC & DC Operating Conditions 3.1 DC Operating Conditions 3.1.1 Recommended DC Operating Conditions(SSTL_1.8) 3.1.2 ODT DC Electrical Characteristics 3.2 DC & AC Logic Input Levels 3.2.1 Input DC Logic Level 3.2.2 Input AC Logic Level 3.2.3 AC Input Test Conditions 3.2.4 Differential Input AC Logic Level 3.2.5 Differential AC Output Parameters 3.3 Output Buffer Levels 3.3.1 Output AC Test Conditions 3.3.2 Output DC Current Drive 3.3.3 OCD default characteristics 3.4 IDD Specifications & Measurement Conditions 3.5 Input/Output Capacitance 4. AC Timing Specifications 5. Package Dimensions Rev. 1.7 / Nov. 2011 3 Free Datasheet http://www.datasheetlist.com/ Release H5PS1G63JFR Series 1. Description 1.1 Device Features & Ordering Information 1.1.1 Key Features • • • • • • • • • • • • • VDD = 1.8 +/- 0.1V VDDQ = 1.8 +/- 0.1V All inputs and outputs are compatible with SSTL_18 interface 8 banks Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) Differential Data Strobe (DQS, DQS) Data outputs on DQS, DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ, DQS and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 3, 4, 5 and 6 supported Programmable additive latency 0, 1, 2, 3, 4 and 5 supported Programmable burst length 4/8 with both nibble sequential and interleave mode Internal eight bank operations with single pulsed RAS Auto refresh and self refresh supported tRAS lockout supported 8K refresh cycles /64ms JEDEC standard 84ball FBGA(x16) Full streng.


H5PS1G63JFR-xxL H5PS1G63JFR-xxJ UPA75HA


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