Document
IRFPS37N50A, SiHFPS37N50A
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) (Max.) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 180 46 71 Single
D
FEATURES
500 0.13
• Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness
Available
RoHS*
COMPLIANT
• Fully Characterized Capacitance and Avalanche Voltage and Current • Effective Coss Specified • Lead (Pb)-free Available
SUPER-247TM
APPLICATIONS
G S D G S N-Channel MOSFET
• Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High Speed Power Switching
TYPICAL SMPS TOPOLOGIES
• Full Bridge Converters • Power Factor Correction Boost
ORDERING INFORMATION
Package Lead (Pb)-free SnPb SUPER-247TM IRFPS37N50APbF SiHFPS37N50A-E3 IRFPS37N50A SiHFPS37N50A
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 1.94 mH, RG = 25 Ω, IAS = 36 A (see fig. 12). c. ISD ≤ 36 A, dI/dt ≤ 145 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply TC = 25 °C EAS IAR EAR PD dV/dt TJ, Tstg VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM LIMIT 500 ± 30 36 23 144 3.6 1260 36 44 446 3.5 - 55 to + 150 300d W/°C mJ A mJ W V/ns °C A UNIT V
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IRFPS37N50A, SiHFPS37N50A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.24 MAX. 40 0.28 °C/W UNIT
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER Static Drain-Source Breakdown Voltage Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf
VGS = 0 V, ID = 250 µA VDS = VGS, ID = 250 µA VGS = ± 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 150 °C VGS = 10 V ID = 22 Ab Ab VDS = 50 V, ID = 22
500 2.0 20
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4.0 ± 100 25 250 0.13 -
V V nA µA Ω S
VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V , f = 1.0 MHz VGS = 0 V VDS = 400 V , f = 1.0 MHz VDS = 0 V to 400 V VGS = 10 V ID = 36 A, VDS = 400 V, see fig. 6 and 13b
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5579 810 36 7905 221 400 23 98 52 80
180 46 71 ns nC pF
VDD = 250 V, ID = 36 A, RG = 2.15 Ω, RD = 7.0 Ω, see fig. 10b
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-
570 8.6
36 A 144 1.5 860 13 V ns µC
G
S
TJ = 25 °C, IS = 36 A, VGS = 0 Vb TJ = 25 °C, IF = 36 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
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