ICS95V860

Integrated Circuit Systems, Inc. ICS95V860 2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz) Recommended Application: DDR Memory Modules / Zero Delay Fan Out Buffer Product Description/Features: Low skew, low jitter PLL clock driver 1 to 13 differential clock distribution (SSTL_2) Feedback pins for input to output synchronization PD# for power management Spread Spectrum-tolerant inputs Auto PD when input signal removed 0°C to 85°C operation Switching Characteristics: CYCLE - CYCLE jitter (>100MHz):<75ps OUTPUT - OUTPUT skew: <70ps DUTY CYCLE: 49% - 51% Functionality INPUTS AVDD PD# GND GND 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) H H L H H X CLK_INT L H X L H <20MHz) OUTPUTS PLL State CLK_INC CLKT CLKC FB_OUTT FB_OUTC H L X H L L H Z L H Z H L Z H L Z L H Z L H Z H L Z H L Z Bypassed/off Bypassed/off off on on off Block Diagram FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1 PD# I2C_SCL, I2C_SDA I2C_A0, I2CA1 Control Logic CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 FB_INT FB_INC CLK_INC CLK_INT CLKT5 CLKC5 PLL CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 CLKT10 CLKC10 CLKT11 CLKC11 CLKT12 CLKC12 0675D—01/07/04 Free Datasheet http://www.nDatasheet.com ICS95V860 Bottom View 1 2 A I2C_A0 CLKC0 B I2C_A1 VSS C FB_OUTT VSS D FB_OUTC VDD E FB_INT FB_INC F AVDD AGND G CLK_INT CLK_INC H CLKT12 VDD J CLKC12 VSS K I2C_SDA VSS L I2C_SCL CLKT11 3 CLKT0 VDD 4 CLKC1 VDD 5 CLKT1 VSS 6 CLKC2 VSS 7 CLKT2 VDD 8 CLKC3 VDD 9 CLKT3 VSS Top View VDD CLKC11 VD...