Document
ST3L01
TRIPLE VOLTAGE REGULATOR
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DUAL INPUT VOLTAGE (12V AND 5V) TRIPLE OUTPUT VOLTAGE (2.6V, 3.3V, 8V) 2.6V GUARANTEED IOUT UP TO 1.2A 3.3V GUARANTEED IOUT UP TO 1.0A 8V GUARANTEED IOUT UP TO 200mA THERMAL AND SHORT CIRCUIT PROTECTION GUARANTEED OPERATING TEMPERATURE RANGE (0°C to 125°C)
SPAK-7L (PowerFlex™)
DESCRIPTION This device contains three voltage regulators, all fixed output voltage, in one 7 pin surface mount package. The first is a 2.6 V regulator to power the integrated controller/µP. The second is a 3.3V regulator to power the read channel chip, and memory chips requiring 3.3V The last is an 8V regulator to power the preamp chip. The bandgap reference, the 8V ground, and the substrate are all tied to a common ground pin, while the 2.6V and 3.3V ground is tied to a separate ground pin.This
SCHEMATIC DIAGRAM
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grounding scheme allows for improved noise isolation between the 8V regulator and the 2.6V and 3.3V regulators.The 2.6V and 3.3V regulators shall be respectively capable of 1.0A and 1.2A. The 8V regulator shall be capable of 200mA. It is housed in the SPAK (PowerFlex™)
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V2.6
March 2002
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ST3L01
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VESD Tstg TJ Supply Voltage ISupply Voltage ESD Tolerance (Human Body Model) Storage Temperature Range Operating Junction Temperature Range Parameter Value 18 18 4 -65 to +150 0 to +150 Unit V V KV °C °C
GENERAL OPERATING CONDITION
Symbol VCC ∆VCC tr tf VDD ∆VDD tr tf TAl VCC Supply Voltage VCC Ripple Rise Time (10% to 90%) referred to VCC Fall Time (90% to 10%) referred to VCC VDD Supply Voltage VDD Ripple Rise Time (10% to 90%) referred to VDD Fall Time (90% to 10%) referred to VDD Operating Ambient Temperature Range Parameter Value 4.75 to 5.25 ±0.15 1 1 10.8 to 13.2 ±0.3 1 Unit V V V
THERMAL DATA
Symbol Rthj-case Parameter Thermal Resistance Junction-case
CONNECTION DIAGRAM (top view)
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0 to 70
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V V V
V V
µs
SPAK-7L 2
Unit °C/W
PIN DESCRIPTION
Pin N° Symbol 1 2 3 4 5 6 7 VO2 VCC GND3 VO3 VDD VO1 Name and Function Second Output Pin: Bypass with a 0.1µF capacitor to GND Input Pin: Bypass with a 0.1µF capacitor to GND VO3 regulators GND pin Third Output Pin: Bypass with a 0.1µF capacitor to GND Input Pin: Bypass with a 0.1µF capacitor to GND First Output Pin: Bypass with a 0.1µF capacitor to GND
GND1,2 VO1 and VO2 regulators GND pin
SPAK-7L
ORDERING INFORMATION
TYPE ST3L01
(*) Available in Tape & Reel with the suffix "R"
SPAK (Power Flex™) 7 leads (*) ST3L01K7
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ST3L01
TYPICAL APPLICATION CIRCUIT
Note: To improve noise figure of the 8V VREG connect this capacitor to the GND8V pin. CCC, CDD, CO1, CO2 and CO3 capacitors must be located not more than 0.5" from the output pins of the device. Form more details about Capacitors read the "Application Hints"
ELECTRICAL CHARACTERISTICS (VCC=5V, VDD=12V, CCC=1µF (Tantalum), C DD=0.1µF (X7R), CO1=CO2=C O3=0.11µF (X7R) Tj=0 to 125°C unless otherwise specified. Typical values are referred at Tj=25°C, IFL1 =1.2A, IFL2 =1.0A, IFL3 =0.2A,
Symbol VO1 Parameter Output Voltage 1 IO1 = 10mA IO1 = 0 to IFL1 Tj = 0 to 125°C VO2 Output Voltage 2 IO2 = 10mA Test Conditions Tj = 25°C VCC = 4.75 to 5.25V IO1 = 0.5A
VDD = 0 to 10.8V IO2 = 0 to IFL2 Tj = 0 to 125°C VO3 Output Voltage 3
VDD = 0 to 10.8V
∆VO ∆VO VD1 VD2 VD3 tTR
Line Regulation 1
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IOL1 IOL2 IOL3 IO1 IO2 IO3
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Load Regulation 1 Dropout Voltage 1 Dropout Voltage 2 Dropout Voltage 3 Transient Response Output 1 Current Limit Output 2 Current Limit Output 3 Current Limit Output 1 Minimum Load Current Output 2 Minimum Load Current Output 3 Minimum Load Current
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IO3 = 10mA
IO3 = 0 to IFL3 Tj = 0 to 125°C IO = 0.01 to IFL IO1 = IFL1 IO2 = IFL2 IO3 = IFL3 (Note 3, 7)
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o s b O Tj = 25°C IO2 = 0.5A Tj = 25°C VCC =±5% (Note 1) (Note 2) (Note 2) (Note 2)
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2.575 2.55 2.2 3.23 3.2 2.92 7.84 7.76
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Min.
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2.6 2.6 3.3 3.3
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Max. 2.626 2.65 2.65 3.37 3.4 3.4
Unit V
V
VCC = 4.75 to 5.25V
8 8 <0.2 <0.4 1.3 1.13 1.6 <1
8.16 8.24
V
VDD = 10.8 to 13.2V VDD =±10%
IO = 10mA
%VO %VO 1.9 1.4 2.2 2.5 2.5 0.5 0 0 0 V V V µs A A A mA mA mA
∆VO = 125mV ∆VO = 165mV ∆VOUT = 400mV (Note 4, 7) (Note 4, 7) (Note 4, 7)
1.5 1.1 0.25
2.1 1.7 0.4
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ST3L01
Symbol CO CCC CDD SVR1 SVR2 SVR3 IVCC IVDD eN ∆VO ∆VO
Parameter Output Capacitor Input Capacitor Input Capacitor Supply Voltage Rejection (VCC to Output 1) Supply Voltage Rejection (VCC to Output 2) Supply Voltage Rejection (VDD to Output 3) VCC Quiescent Current VDD Quiescent Current Output Noise Temperature Stability Long Term Stability (Note 5, 7) (Note 5) (Note 5)
Test Conditions
Min. 0.1 1.0 0.1
Typ.
Max.
Unit µF µF µF
RegTherm Therma Regulation
IOUT.