Document
A25L020/A25L010/A25L512 Series
2Mbit / 1Mbit / 512Kbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
Document Title 2Mbit /1Mbit /512Kbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors Revision History
Rev. No.
1.0 1.1 1.2 1.3 1.4 1.5
History
Initial issue Add 8-pin TSSOP package type Add the spec. of ICC3 for 33MHz Modify DC/AC Characteristics Modify AC Characteristics Add packing description in Part Numbering Scheme P30: Change Data Retention and Endurance value from Max. to Min. P37: Add A25L512V-UF, A25L010V-UF and A25L020V-UF in the ordering information
Issue Date
February 27, 2008 September 2, 2008 January 9, 2009 April 21, 2009 April 30, 2010 October 20, 2010
Remark
Final
1.6 1.7 1.8 1.9 2.0
Add 8-pin USON (2*3mm) package type P33: Modify the fR to 66MHz (Max.) Add 8-pin WSON (6*5mm) package type P31 : Add the typical ICC3 @ 100Mhz / 50Mhz / 33Mhz Add typical ICC4 P28, 29 : Update power-up and power-down timing waveform P31: Modify DC Characteristics
December 23, 2010 January 31, 2011 October 28, 2011 March 30, 2012 May 9, 2012
(May, 2012, Version 2.0)
AMIC Technology Corp.
Free Datasheet http://www.Datasheet4U.com
A25L020/A25L010/A25L512 Series
2Mbit / 1Mbit / 512Kbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
FEATURES
Family of Serial Flash Memories - A25L020: 2M-bit /256K-byte - A25L010: 1M-bit /128K-byte - A25L512: 512K-bit /64K-byte Flexible Sector Architecture with 4KB sectors - Sector Erase (4K-bytes) in 0.2s (typical) - Block Erase (64K-bytes) in 0.5s (typical) Page Program (up to 256 Bytes) in 2ms (typical) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 100MHz Clock Rate (maximum) Deep Power-down Mode 15µA (Max.) Stand-by current 15µA (Max.) Electronic Signatures - JEDEC Standard Two-Byte Signature A25L020 (3012h) A25L010 (3011h) A25L512 (3010h) - RES Instruction, One-Byte, Signature, for backward compatibility A25L020 (11h) A25L010 (10h) A25L512 (05h) Package options - 8-pin SOP (150/209mil), 8-pin DIP (300mil), 8-pin TSSOP (A25L010V-F/A25L512V-F), 8-pin USON (2*3mm) and 8-pin WSON (6*5mm) - All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25L020/A25L010/A25L512 are 2M/1M/512K bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4/2/1(A25L020/A25L010/A25L512) blocks, each containing 16 sectors. Each sector is composed of 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024/512/256 (A25L020/A25L010/A25L512) pages, or 262,144/131,072/ 65,536 (A25L020/A25L010/A25L512) bytes. The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction, or a sector at a time, using the Sector Erase instruction.
Pin Configurations
SOP8 Connections
A25L020/ A25L010/ A25L512 S DO W VSS 1 2 3 4 8 7 6 5 VCC HOLD C DIO
DIP8 Connections
A25L020/ A25L010/ A25L512 S DO W VSS 1 2 3 4 8 7 6 5 VCC HOLD C DIO
(May, 2012, Version 2.0)
1
AMIC Technology Corp.
Free Datasheet http://www.Datasheet4U.com
A25L020/A25L010/A25L512 Series
Pin Configurations (Continued)
TSSOP8 Connections
A25L010/ A25L512 S DO W VSS 1 2 3 4 8 VCC 7 HOLD 6 C 5 DIO
USON8/WSON8 Connections
A25L020/ A25L010/ A25L512 S DO W VSS 1 2 3 4 8 7 6 5 VCC HOLD C DIO
Block Diagram
HOLD W S C DIO DO I/O Shift Register
Control Logic
High Voltage Generator
Address register and Counter
256 Byte Data Buffer
Status Register
3FFFFh (2M), 1FFFFh (1M) FFFFh (512K) Y Decoder Size of the memory area
000FFh 00000h 256 Byte (Page Size) X Decoder
(May, 2012, Version 2.0)
2
AMIC Technology Corp.
Free Datasheet http://www.Datasheet4U.com
A25L020/A25L010/A25L512 Series
Pin Descriptions
Pin No. C DIO DO Serial Clock Serial Data Input 1 Serial Data Output 2 Chip Select Write Protect Hold Supply Voltage Ground
VSS DIO C S W HOLD
A25L020/ A25L010/ A25L512
Logic Symbol
Description
VCC
DO
S
W
HOLD
VCC VSS
Notes: 1. The DIO is also used as an output pin when the Fast Read Dual Output instruction and the Fast Read Dual Input-Output instruction are executed. 2. The DO is also used as an input pin when the Fast Read Dual Input-Output instruction is executed.
SIGNAL DESCRIPTION
Serial Data Output (DO). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). The DO pin is also used as an input pin when the Fast Read Dual Input-Output instruction is executed. Serial Data Input (DIO). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). The DIO pin is also used as an output pin when the Fast Read Dual Output instruction and the Fast Rea.