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NPCT42x Dataheets PDF



Part Number NPCT42x
Manufacturers nuvoTon
Logo nuvoTon
Description Trusted Platform Module - TPM
Datasheet NPCT42x DatasheetNPCT42x Datasheet (PDF)

NPCT42x Trusted Platform Module (TPM) Preliminary March 2011 Revision 1.1 NPCT42x Trusted Platform Module (TPM) General Description The NPCT42x single-chip Trusted Platform Module (TPM) is a family of third-generation, Nuvoton SafeKeeper technology devices. The devices implement the Trusted Computing Group (TCG) version 1.2 specifications for PC-Client TPM. The NPCT42x devices are designed to reduce system boot time and Trusted OS loading time. They provide a solution for PC security for a wi.

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NPCT42x Trusted Platform Module (TPM) Preliminary March 2011 Revision 1.1 NPCT42x Trusted Platform Module (TPM) General Description The NPCT42x single-chip Trusted Platform Module (TPM) is a family of third-generation, Nuvoton SafeKeeper technology devices. The devices implement the Trusted Computing Group (TCG) version 1.2 specifications for PC-Client TPM. The NPCT42x devices are designed to reduce system boot time and Trusted OS loading time. They provide a solution for PC security for a wide range of PC applications. The NPCT42x family of devices are Microsoft Windows compliant and are supported by Linux kernel v2.6.18 and higher. Bus Interface ■ LPC Bus Interface — Based on Intel’s LPC Interface Specification Revision 1.1, August 2002 — TPM 1.2 Interface (TIS) Clocking and Supply ■ ■ On-Chip Clock Generator Power Supply — 3.3V supply operation — Separate pins for main (VDD) and standby (VSB) power supplies — Low standby power consumption Features General ■ Single-chip TPM solution — No external parts required Compatible with TPM Main Specification Version 1.2 Revision 116 and PC Client Specific TPM Interface Specification Version 1.21 Revision 72 Host Interface — TPM 1.2 standard interface (TIS) with five localities — Supports legacy locality by using TIS protocol with I/O mapped registers Secure General-Purpose I/O (GPIO) — Five GPIO pins — I/O pins individually configured as input or output — Configurable internal pull-up resistors — TCG 1.2-defined interface — Dedicated Physical Presence (PP) pin with configurable pull-up or pull-down resistor Tick Counter Software ■ ■ ■ ■ ■ TPM BIOS drivers: Memory Absent (MA) and Memory Present (MP) TPM Device Driver for Microsoft Windows NTRU Cryptosystems (acquired by Security Innovation) Core TCG Software Stack (CTSS) Wave Systems Cryptographic Service Provider (CSP) with either EMBASSY® Security Center (ESC) or EMBASSY Trust Suite (ETS) OEM Edition ■ ■ ■ System Block Diagram Chipset LPC Bus Physical Presence NPCT42x SuperI/O GPIO © 2011 Nuvoton Technology Corporation www.nuvoton.com Free Datasheet http://www.Datasheet4U.com NPCT42x Features (Continued) Product-Specific Information The following table lists the available products in the NPCT42x family. Software TPM BIOS drivers NTRU Cryptosystems CTSS Wave Systems CSP and ESC Wave Systems ETS OEM Edition NPCT42xA ✔ NPCT42xB ✔ ✔ NPCT42xC ✔ ✔ ✔ NPCT42xD1 ✔ ✔ ✔ ✔ NPCT42xL ✔ 1. Restricted availability; please contact your nearest Nuvoton office. See back cover for details. www.nuvoton.com 2 Revision 1.1 Free Datasheet http://www.Datasheet4U.com NPCT42x Datasheet Revision Record Revision Date March 2011 May 2011 Status Revision 1.0 Preliminary NPCT42x Datasheet. Revision 1.1 NPCT42xL added. Comments Revision 1.1 3 www.nuvoton.com Free Datasheet http://www.Datasheet4U.com NPCT42x Table of Contents Features.............................................................................................................................................................. 1 Product-Specific Information............................................................................................................................... 2 Datasheet Revision Record ............................................................................................................................... 3 1.0 Signal/Pin Connection and Description 1.1 1.2 1.3 CONNECTION DIAGRAM ........................................................................................................... 6 BUFFER TYPES AND SIGNAL/PIN DIRECTORY ...................................................................... 6 SIGNAL/PIN DESCRIPTIONS ..................................................................................................... 7 1.3.1 LPC Interface ................................................................................................................. 7 1.3.2 Inputs and Outputs ....................................................................................................... 7 1.3.3 Configuration Straps and Testing .................................................................................. 7 1.3.4 Power and Ground ........................................................................................................ 8 1.3.5 Not Connected ............................................................................................................... 8 INTERNAL PULL-UP AND PULL-DOWN RESISTORS .............................................................. 8 1.4 2.0 Trusted Platform Module (TPM) Overview 2.1 2.2 2.3 SYSTEM CONNECTIONS .......................................................................................................... 9 POWER MANAGEMENT (PM) .................................................................................................... 9 HOST INTERFACE ..................................................................................................................... 9 3.0.


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