9LPRS501 Datasheet: ICS9LPRS501





9LPRS501 ICS9LPRS501 Datasheet

Part Number 9LPRS501
Description ICS9LPRS501
Manufacture IDT
Total Page 27 Pages
PDF Download Download 9LPRS501 Datasheet PDF

Features: Datasheet 64-PIN CK505 W/FULLY INTEGRAT ED VOLTAGE REGULATOR + INTEGRATED SERIE S RESISTOR Recommended Application: CK5 05 compliant clock with fully integrate d voltage regulator and Internal series resistor on differential outputs, PCIe Gen 1 compliant ICS9LPRS501 Key Spec ifications: • • • • CPU outputs cycle-cycle jitter < 85ps SRC output c ycle-cycle jitter < 125ps PCI outputs c ycle-cycle jitter < 250ps +/- 100ppm fr equency accuracy on CPU & SRC clocks O utput Features: • • • • • • • • 2 - CPU differential low power push-pull pairs 10 - SRC differential low power push-pull pairs 1 - CPU/SRC s electable differential low power push-p ull pair 1 - SRC/DOT selectable differe ntial low power push-pull pair 5 - PCI, 33MHz 1 - PCI_F, 33MHz free running 1 - USB, 48MHz 1 - REF, 14.318MHz • • • • • Features/Benefits: Does n ot require external pass transistor for voltage regulator Integrated series re sistors on differential outputs, Zo=50Ω Supports spread spectrum modulation, default is 0.5% down.

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Datasheet
64-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR + INTEGRATED SERIES RESISTOR
ICS9LPRS501
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator and Internal series resistor on differential outputs,
PCIe Gen 1 compliant
Output Features:
• 2 - CPU differential low power push-pull pairs
• 10 - SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull
pair
• 1 - SRC/DOT selectable differential low power push-pull
pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on CPU & SRC
clocks
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
• Integrated series resistors on differential outputs,
Zo=50Ω
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal
load caps are required for frequency tuning
• One differential push-pull pair selectable between
SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
FSLC2
B0b7
FSLB1
B0b6
FSLA1
B0b5
CPU
MHz
SRC
MHz
PCI REF
MHz MHz
00
0 266.66
00
1 133.33
01
01
0 200.00
1 166.66 100.00 33.33 14.318
10
0 333.33
10
1 100.00
11
11
0 400.00
1
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
USB
MHz
48.00
DOT
MHz
96.00
TSSOP Pin Configuration
PCI0/CR#_A 1
VDDPCI 2
PCI1/CR#_B 3
PCI2/TME 4
PCI3 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96_IO 12
DOTT_96/SRCT0 13
DOTC_96/SRCC0 14
GND 15
VDD 16
SRCT1/SE1 17
SRCC1/SE2 18
GND 19
VDDPLL3_IO 20
SRCT2/SATAT 21
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
SRCC3/CR#_D 25
VDDSRC_IO 26
SRCT4 27
SRCC4 28
GNDSRC 29
SRCT9 30
SRCC9 31
SRCC11/CR#_G 32
IDTTM/ICSTM 64-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1
64 SCLK
63 SDATA
62 REF0/FSLC/TEST_SEL
61 VDDREF
60 X1
59 X2
58 GNDREF
57 FSLB/TEST_MODE
56 CK_PWRGD/PD#
55 VDDCPU
54 CPUT0
53 CPUC0
52 GNDCPU
51 CPUT1_F
50 CPUC1_F
49 VDDCPU_IO
48 NC
47 CPUT2_ITP/SRCT8
46 CPUC2_ITP/SRCC8
45 VDDSRC_IO
44 SRCT7/CR#_F
43 SRCC7/CR#_E
42 GNDSRC
41 SRCT6
40 SRCC6
39 VDDSRC
38 PCI_STOP#/SRCT5
37 CPU_STOP#/SRCC5
36 VDDSRC_IO
35 SRCC10
34 SRCT10
33 SRCT11/CR#_H
1121G—05/19/11
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