Datasheet
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Recommended Application:
CK505...
Datasheet
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR + INTEGRATED SERIES RESISTOR
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator and Internal series resistor on differential outputs, PCIe Gen 1 compliant
ICS9LPRS502
Key Specifications:
CPU outputs cycle-cycle jitter < 85ps SRC output cycle-cycle jitter < 125ps PCI outputs cycle-cycle jitter < 250ps +/- 100ppm frequency accuracy on CPU & SRC clocks
Output Features:
2 - CPU differential low power push-pull pairs 7 - SRC differential low power push-pull pairs 1 - CPU/SRC selectable differential low power push-pull pair 1 - SRC/DOT selectable differential low power push-pull pair 5 - PCI, 33MHz 1 - PCI_F, 33MHz free running 1 - USB, 48MHz 1 - REF, 14.318MHz
Features/Benefits:
Does not require external pass
transistor for voltage
regulator Integrated series resistors on differential outputs, Zo=50W Supports spread spectrum modulation, default is 0.5% down spread Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning One differential push-pull pair selectable between SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
FSLC B0b7 0 0 0 0 1 1 1 1
2
Pin Configuration
USB MHz DOT MHz
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a ...