SN74LS155 DEMULTIPLEXER Datasheet

SN74LS155 Datasheet, PDF, Equivalent


Part Number

SN74LS155

Description

DUAL 1-OF-4 DECODER / DEMULTIPLEXER

Manufacture

ON Semiconductor

Total Page 4 Pages
Datasheet
Download SN74LS155 Datasheet


SN74LS155
SN74LS155
DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
The SN54 / 74LS156 is a high speed Dual 1-of-4
Decoder/Demultiplexer. This device has two decoders with common
2-bit Address inputs and separate gated Enable inputs. Decoder “a”
has an Enable gate with one active HIGH and one active LOW input.
Decoder “b” has two active LOW Enable inputs. If the Enable
functions are satisfied, one output of each decoder will be LOW as
selected by the address inputs. The LS156 has open collector outputs
for wired-OR (DOT-AND) decoding and function generator
applications.
The LS156 is fabricated with the Schottky barrier diode process for
high speed and are completely compatible with all Motorola TTL
families.
Schottky Process for High Speed
Multifunction Capability
Common Address Inputs
True or Complement Data Demultiplexing
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC Eb Eb A0 O3b O2b O1b O0b
16 15 14 13 12 11 10 9
NOTE:
The Flatpak version
has the same pinouts (Connection
Diagram) as the Dual In-Line Pack-
age.
1 2 3 4 56 78
Ea Ea A1 O3a O2a O1a O0a GND
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DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
LS156-OPEN-COLLECTOR
LOW POWER SCHOTTKY
16
1
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
16
1
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
PIN NAMES
LOADING (Note a)
HIGH
LOW
A0, A1
Ea, Eb
Ea
O0 O3
Address Inputs
Enable (Active LOW) Inputs
Enable (Active HIGH) Input
Active LOW Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 μA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges. The HIGH level drive for the LS156 must be established by an
external resistor.
© Semiconductor Components Industries, LLC, 2006
June, 2006 Rev. 7
1
1 2 13 3 14 15
E
DECODER a
012
A0
A1
3
A0 E
A1 DECODER b
0 123
765 4
9 10 11 12
VCC = PIN 16
GND = PIN 8
Publication Order Number:
SN74LS155/D
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SN74LS155
LOGIC DIAGRAM
SN74LS155
SN54 / 74LS156
Ea Ea
12
A0 A1
13 3
Eb Eb
14 15
VGCNCD==PPININ186
= PIN NUMBERS
7
O0a
6
O1a
5
O2a
4
O3a
9
O0b
10
O1b
11 12
O2b O3b
FUNCTIONAL DESCRIPTION
The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with
common Address inputs and separate gated Enable inputs.
When enabled, each decoder section accepts the binary
weighted Address inputs (A0, A1) and provides four mutually
exclusive active LOW outputs (O0 O3). If the Enable
requirements of each decoder are not met, all outputs of that
decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (EaEa). In demultiplexing
applications, Decoder “a” can accept either true or
complemented data by using the Ea or Ea inputs respectively.
The enable gate for Decoder “b” requires two active LOW
inputs (EbEb). The LS155 or LS156 can be used as a 1-of-8
Decoder/Demultiplexer by tying Ea to Eb and relabeling the
common connection as (A2). The other Eb and Ea are
connected together to form the common enable.
The LS156 can be used to generate all four minterms of
two variables. These four minterms are useful in some
applications replacing multiple gate functions as shown in
Fig. a. The LS156 has the further advantage of being able to
TRUTH TABLE
ADDRESS ENABLE “a”
OUTPUT “a”
A0 A1 Ea Ea O0 O1 O2
XXL XHHH
XXXHHHH
L LH L LHH
HLHLHLH
L HH L HH L
HHH L HHH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A0 + A1) (E + A0 + A1) (E + A0 + A1)
(E + A0 + A1)
where E = Ea + Ea; E = Eb + Eb
EE
A0
A1
O0
A0
A1
O0
EE
A0 O1 A0
A1 A1
EE
A0 O2 A0
A1 A1
EE
A0 O3 A0
A1 A1
O1
O2
O3
Figure a
ENABLE “b”
OUTPUT “b”
O3 Eb Eb O0 O1 O2 O3
HH X H HH H
HXHHHHH
HL L L HHH
HL LH LHH
HL LHHLH
L L LHHH L
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2
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Features SN74LS155 DUAL 1-OF-4 DECODER/ DEMULTIPL EXER The SN54 / 74LS156 is a high speed Dual 1-of-4 Decoder/Demultiplexer. Thi s device has two decoders with common 2 -bit Address inputs and separate gated Enable inputs. Decoder “a” has an E nable gate with one active HIGH and one active LOW input. Decoder “b” has two active LOW Enable inputs. If the En able functions are satisfied, one outpu t of each decoder will be LOW as select ed by the address inputs. The LS156 has open collector outputs for wired-OR (D OT-AND) decoding and function generator applications. The LS156 is fabricated with the Schottky barrier diode process for high speed and are completely comp atible with all Motorola TTL families. • Schottky Process for High Speed • Multifunction Capability • Common Ad dress Inputs • True or Complement Dat a Demultiplexing • Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts http://onsemi.com DUAL 1-OF-4 DECODER/ DEMULTIPLEXER LS156-OPEN-COLLECTOR LOW POWER SCHOTTKY 16 J S.
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