Document
STA559BW
5 V, 2 A, 2.1 channel high-efficiency digital audio system Sound Terminal®
Datasheet - production data
Audio presets: – 15 preset crossover filters – 5 preset anti-clipping modes – Preset night-time listening mode Individual channel soft/hard mute Independent channel volume and DSP bypass
PowerSSO-36 with exposed pad down (EPD)
2-channel I²S input data interface Input and output channel mapping Automatic invalid-input detect Mute Automatic zero-detect mute
Features
Wide-range supply voltage, 4.5 V to 16 V Three power output configurations: – 2 channels of ternary PWM (2 x 3 W into 4 at 5 V) + PWM output – 2 channels of ternary PWM (2 x 3 W into 4 at 5 V) + ternary stereo line-out – 2.1 channels of binary PWM (left, right, LFE) (2 x 0.7 W + 1 x 3 W into 4 at 5 V) (2 x 1.4 W + 1 x 6 W into 2 at 5 V) FFX with 100-dB SNR and dynamic range Selectable 32- to 192-kHz input sample rates I²C control with selectable device address Digital gain/attenuation +48 dB to -80 dB with 0.5-dB/step resolution Soft volume update Individual channel and master gain/attenuation Two independent limiters/compressors Dynamic range compression or anti-clipping modes
Up to 4 user-programmable biquads/channel Three coefficients banks for EQ presets storing with fast recall via I²C interface Bass/treble tones and de-emphasis control Selectable high-pass filter for DC blocking Advanced AM interference frequency switching and noise suppression modes Selectable high- or low-bandwidth noise-shaping topologies Selectable clock input ratio Thermal overload and short-circuit protection embedded Video apps: 576 x fS input mode supported
Table 1. Device summary
Order code STA559BWTR Package Packaging
PowerSSO-36 EPD Tape and reel
February 2014
This is information on a product in full production.
DocID18190 Rev 2
1/67
www.st.com
http://www.Datasheet4U.com
Contents
STA559BW
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 3.4 3.5 3.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 12 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 13 Power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 5
Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I²C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 5.1.2 5.1.3 5.1.4 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 5.3
Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 5.3.2 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.1 5.4.2 5.4.3 5.4.4 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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