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HY510N
PC POWER SUPPLY SUPERVISOR
Data Sheet
REV. 1.30 September 21, 2004
The information in this document is subject to change without notice.
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TEL:886-2-23775117 FAX:886-2-23773189 Email:
[email protected]
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HY510N
Rev. 1.30
GENERAL DESCRIPTION
The HY510N provides protection circuits, power good output (PGO), fault protection latch (FPL_N), and a protection detector function (PDON_N) control. It can minimize external components of switching power supply systems in personal computer. The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level. The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level. When OVD or UVD detect the fault voltage level, the FPL_N is latched HIGH and PGO go low. The latch can be reset by PDON_N goo HIGH. There is 2.4 ms delay time for PDON_N turn off FPL_N. When OVD and UVD detect the right voltage level, the power good output (PGO) will be issue.
FEATURES
• • • • • • • • • The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level. The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level. Both of the power good output (PGO) and fault protection latch (FPL_N) are Open Drain Output. 75 ms time delay for UVD. 300 ms time delay for PGO. 38 ms for PDON_N input signal De–bounce. 73 us for internal signal De–glitches. 2.4 ms time delay for PDON_N turn-off FPL_N. ESD voltage up to 4000V as tested under MIL–STD–883D, Method 3015.7.
PIN ASSIGNMENT AND PACKAGE TYPE
PGI GND FPL_N PDON_N
1 2 3 4
8 7 6 5
PGO VCC V5 V33
ORDERING INFORMATION PACKAGE
8–Pin Plastic DIP 8–Pin Plastic SOP HY510N–N080WT HY510N–S080WT Lead–Free¡] Pb¡^ HY510N–N080WT Pb HY510N–S080WT Pb ¡° The Top-Side Marking would be added a dot¡]¡´¡^in the right side for lead-free package. PIN DESCRIPTION Description Pin No. Pin Name TYPE 1 PGI I power good input pin 2 GND P Ground 3 FPL_N O fault protection latch output pin(open drain output) 4 PDON_N I protection detector function ON/OFF control input pin 5 V33 I 3.3V input pin 6 V5 I 5V input pin 7 VCC I Supply voltage / 12V input pin 8 PGO O power good output pin(open drain output)
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HY510N
Rev. 1.30
FUNCTION TABLE
PGI < 0.95V < 0.95V < 0.95V 0.95 < PGI < 1.2 0.95 < PGI < 1.2 0.95 < PGI < 1.2 PGI > 1.2 PGI > 1.2 PGI > 1.2 x x = don’t care PDON_N L L L L L L L L L H UV no no yes no no yes no no yes x OV no yes no no yes no no yes no x FPL_N L H L L H H L H H H PGO L L L L L L H L L L
BLOCK DIAGRAM
EN0158A_WT7510 BLOCK DIAGRAM
VCC
Power On Reset
150uA
POR LVRST
VCC Low Voltage
Clock Generator
CLK PWR
3.6V
CLK PWR RST 38ms debounce - UN CLK PWR 75 ms delay
CLK 2.4ms delay
PWR
PDON_N
clr
V33
+
+
- OV
clr
V5
+
- UN
CLK RST
R FPL_N Q
+
- OV
73us debounce
S
VCC
+
- OV
CLK RST 73us debounce
CLK 300ms delay
VCC
PGO
PGI
+
- UN
clr
1.2V
+
-
0.95V
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HY510N
Rev. 1.30
RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage, VCC Input voltage Output voltage Operating temperature Output sink current Supply voltage rising time PDON_N, V5, V33, PGI FPL_N PGO -40 FPL_N PGO 1 Conditions Min. 4 Typ. 12 Max. 15 7 15 7 125 30 10 Unit V V V V ¢J mA mA ms
ELECTRICAL CHARACTERISTICS, at Ta=25°C and VCC=5V.
Over Voltage Detection Parameter Over voltage threshold Condition V33 V5 Vcc / V12 ILEAKAGE Leakage current (FPL_N) VOL Low level output voltage (FPL_N) Min. 3.7 5.7 12.8 Typ. 3.9 6.1 13.4 5 0.3 0.7 Typ. 2.2 3.5 1.20 0.95 5 0.4 Typ. 150 Max. 4.1 6.5 13.9 Unit V V V uA V
V(FPL_N) = 5V Isink 10mA Isink 30mA Condition Min. 2.0 3.3 1.16 0.90
PGI and PGO Parameter Under voltage threshold Input threshold voltage(PGI) V33 V5 PGI1 PGI2 PGO = 5V Max. 2.4 3.7 1.24 1.00 Unit V V V uA V Max. Unit uA V V Unit mA V Unit mS mS mS uS mS mS
ILEAKAGE Leakage current(PGO) VOL Low level output voltage(PGO) PDON_N Parameter Condition Input pull-up current PDON_N= 0V High-level input voltage Low-level input voltage TOTAL DEVICE Parameter Condition Icc Supply current PDON _N= 5V Vcc low voltage SWITCHING CHARACTERISTICS, Vcc=5V Parameter Condition tdb1 De-bounce time (PDON_N) tdleay1 Delay time (PGI to PGO) tdb2 De-bounce time (PDON_N) tg De-glitch time tdelay2 PDON_N to FPL_N delay time tdelay3 Internal UVD delay time FPL_N go low every time PGI 0.95V
Min. 2.0
0.8 Min. Typ. 3 Min. Typ. Max. 32 38 61 200 300 490 32 38 61 63 73 120 tdb2+2.0 tdb2+2.4 tdb2+3.8 & 65 75 122 > Max. 1
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HY510N
Rev. 1.30
APPLICATION CIRCUIT
5V
5V
0.01uF PGI 1 2 3 470 PDON_N 4
PGI GND FPL_N PDON_N
PGO VCC V5 V33
8 7 6 5
12V 5V 3.3V VSB
0.01uF
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HY510N
Rev. 1.30
APPLICATION TIMMING
1.) PGI (UNDER_VOLTAGE)¡G
PDON_N tdelay2 FPL_N PGO PGI tdb1 tdelay1+tg tdb2
PDON_N tdelay2 FPL_N PGO PGI tdb1 tdelay1+tg tdelay1+tg tdb2
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HY510N
Rev. 1.30
2.) V33, V5 (UNDER_VOLTAGE)¡G
PDON_N tdelay2 .