Jitter Cleaner. LMK04800 Datasheet

LMK04800 Cleaner. Datasheet pdf. Equivalent

LMK04800 Datasheet
Recommendation LMK04800 Datasheet
Part LMK04800
Description Low-Noise Clock Jitter Cleaner
Feature LMK04800; L M K 0 4 8 X X E V A L U A T I O N B O A R D O P E R A T I N G I N S T R U C T I O N S LMK0480.
Manufacture National Semiconductor
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National Semiconductor LMK04800
LMK048XX EVALUATION BOARD OPERATING INSTRUCTIONS
LMK04800 Family
Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
LMK048xx Evaluation Board Operating Instructions
National Semiconductor Corporation
High Speed Products Division
Precision Timing Devices
January 2012
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National Semiconductor LMK04800
LMK048XX EVALUATION BOARD OPERATING INSTRUCTIONS
Table of Contents
TABLE OF CONTENTS.............................................................................................................................................. 2
GENERAL DESCRIPTION.......................................................................................................................................... 4
EVALUATION BOARD KIT CONTENTS ..................................................................................................................................4
AVAILABLE LMK048XX EVALUATION BOARDS.....................................................................................................................4
AVAILABLE LMK04800 FAMILY DEVICES ...........................................................................................................................4
QUICK START ......................................................................................................................................................... 5
DEFAULT CODELOADER MODES FOR EVALUATION BOARDS....................................................................................................6
EXAMPLE: USING CODELOADER TO PROGRAM THE LMK04808B ........................................................................... 7
1. START CODELOADER 4 APPLICATION..............................................................................................................................7
2. SELECT DEVICE ..........................................................................................................................................................7
3. PROGRAM/LOAD DEVICE.............................................................................................................................................8
4. RESTORING A DEFAULT MODE......................................................................................................................................8
5. VISUAL CONFIRMATION OF FREQUENCY LOCK..................................................................................................................9
6. ENABLE CLOCK OUTPUTS.............................................................................................................................................9
PLL LOOP FILTERS AND LOOP PARAMETERS......................................................................................................... 11
PLL 1 LOOP FILTER ......................................................................................................................................................11
122.88 MHz VCXO PLL ........................................................................................................................................11
PLL2 LOOP FILTER .......................................................................................................................................................12
Integrated VCO PLL ............................................................................................................................................12
EVALUATION BOARD INPUTS AND OUTPUTS....................................................................................................... 13
RECOMMENDED TEST EQUIPMENT...................................................................................................................... 21
PROGRAMMING 0-DELAY MODE IN CODELOADER .............................................................................................. 22
OVERVIEW..................................................................................................................................................................22
DUAL LOOP 0-DELAY MODE EXAMPLES ...........................................................................................................................22
Programming Steps............................................................................................................................................22
Details ................................................................................................................................................................22
SINGLE LOOP 0-DELAY MODE EXAMPLES .........................................................................................................................24
Programming Steps............................................................................................................................................24
Details ................................................................................................................................................................24
APPENDIX A: CODELOADER USAGE...................................................................................................................... 26
PORT SETUP TAB .........................................................................................................................................................26
CLOCK OUTPUTS TAB ...................................................................................................................................................27
PLL1 TAB...................................................................................................................................................................29
Setting the PLL1 VCO Frequency and PLL2 Reference Frequency.......................................................................30
PLL2 TAB...................................................................................................................................................................31
BITS/PINS TAB ............................................................................................................................................................32
REGISTERS TAB............................................................................................................................................................37
APPENDIX B: TYPICAL PHASE NOISE PERFORMANCE PLOTS................................................................................. 38
PLL1 .........................................................................................................................................................................38
122.88 MHz VCXO Phase Noise ..........................................................................................................................38
Clock Output Measurement Technique..............................................................................................................39
Buffered OSCout Phase Noise.............................................................................................................................39
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National Semiconductor LMK04800
LMK048XX EVALUATION BOARD OPERATING INSTRUCTIONS
CLOCK OUTPUTS (CLKOUT) ...........................................................................................................................................40
LMK04808B CLKout Phase Noise........................................................................................................................40
LMK04808B OSCout Phase Noise .......................................................................................................................42
LMK04806B CLKout Phase Noise........................................................................................................................43
LMK04806B OSCout Phase Noise .......................................................................................................................45
LMK04803B CLKout Phase Noise........................................................................................................................46
LMK04803B OSCout Phase Noise .......................................................................................................................48
APPENDIX C: SCHEMATICS ................................................................................................................................... 49
POWER SUPPLIES .........................................................................................................................................................49
LMK048XXB DEVICE WITH LOOP FILTER AND CRYSTAL CIRCUITS..........................................................................................50
REFERENCE INPUTS (CLKIN0 & CLKIN1), EXTERNAL VCXO (OSCIN) & VCO CIRCUITS, AND OSCOUT1 OUTPUT .........................51
CLOCK OUTPUTS (OSCOUT0, CLKOUT0 TO CLKOUT3) ......................................................................................................52
CLOCK OUTPUTS (CLKOUT4 TO CLKOUT7) ......................................................................................................................53
CLOCK OUTPUTS (CLKOUT8 TO CLKOUT11) ....................................................................................................................54
UWIRE HEADER, LOGIC I/O PORTS AND STATUS LEDS........................................................................................................55
USB INTERFACE...........................................................................................................................................................56
APPENDIX D: BILL OF MATERIALS ........................................................................................................................ 57
APPENDIX E: PCB LAYERS STACKUP..................................................................................................................... 66
APPENDIX F: PCB LAYOUT.................................................................................................................................... 67
LAYER #1 TOP ..........................................................................................................................................................67
LAYER #2 RF GROUND PLANE (INVERTED).....................................................................................................................68
LAYER #3 VCC PLANES ...............................................................................................................................................69
LAYER #4 GROUND PLANE (INVERTED)..........................................................................................................................70
LAYER # 5 VCC PLANES 2............................................................................................................................................71
LAYER #6 BOTTOM....................................................................................................................................................72
LAYERS #1 AND 6 TOP AND BOTTOM (COMPOSITE).........................................................................................................73
APPENDIX G: PROPERLY CONFIGURING LPT PORT ............................................................................................... 74
LPT DRIVER LOADING...................................................................................................................................................74
CORRECT LPT PORT/ADDRESS .......................................................................................................................................74
CORRECT LPT MODE....................................................................................................................................................75
APPENDIX H: TROUBLESHOOTING INFORMATION ............................................................................................... 76
1) CONFIRM COMMUNICATIONS ...............................................................................................................................76
2) CONFIRM PLL1 OPERATION/LOCKING ....................................................................................................................76
3) CONFIRM PLL2 OPERATION/LOCKING ....................................................................................................................77
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