CY7C371

7c371: Tuesday, May 26, 1992 Revision: August 9, 1995 CY7C371 UltraLogict 32ĆMacrocell Flash CPLD Features Functional Description D D D D D 32 macrocells in two logic blocks 32 I/O pins 6 dedicated inputs including 2 clock pins No hidden delays High speed Ċ fMAX Ċ tPD= Ċ tS Ċ tCO= = 143 MHz 8.5 ns The CY7C371 is a Flash erasable Complex Programmable Logic Device (CPLD) and is part of the FLASH370 family of highĆdenĆ sity, highĆspeed CPLDs. Like all members of the FLASH370 family, the CY7C371 is designed to bring the ease of use and high performance of the 22V10 to highĆdensity CPLDs. The 32 macrocells in the CY7C371 are diĆ vided between two logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 architecĆ ture are connected with an extremely fast and predictable routing resourceĊthe Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routĆ ability, speed, and a uniform delay to the interconnect. Like all members of the FLASH370 family, the CY7C371 is rich in I/O resources. Each macrocell in the device features an associated I/O pin, resulting in 32 I/O pins on the CY7C371. In addition, there are four dedicated inputs and two input/clock pins. Finally, the CY7C371 features a very simĆ ple timing model. Unlike other highĆdenĆ sity CPLD architectures, there are no hidĆ den speed delays such as fanout effects, inĆ terconnect delays, or expander delays....