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2032E Dataheets PDF



Part Number 2032E
Manufacturers LatticeSemiconductor
Logo LatticeSemiconductor
Description In-SystemProgrammableSuperFASTHighDensityPLD
Datasheet 2032E Datasheet2032E Datasheet (PDF)

ispLSI 2032E In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 225 MHz Maximum Operating Frequen.

  2032E   2032E


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ispLSI 2032E In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functionally and JEDEC Upward Compatible with ispLSI 2032 Devices • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 225 MHz Maximum Operating Frequency — tpd = 3.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O (48-Pin Package Only) Supports Mixed Voltage Systems — PCI Compatible Outputs (48-Pin Package Only) — Open-Drain Output Option — Electrically Erasable and Reprogrammable — Non-Volatile — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms 2 ® ® Functional Block Diagram A0 Output Routing Pool (ORP) Input Bus A2 GLB Logic Array D Q D Q A5 D Q A3 A4 0139Bisp/2000 Description The ispLSI 2032E is a High Density Programmable Logic Device. The device contains 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2032E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 2032E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2032E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. A7 (see Figure 1). There are a total of eight GLBs in the ispLSI 2032E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. The device also has 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com June 1999 2032e_03 1 Input Bus A1 D Q A6 Output Routing Pool (ORP) Global Routing Pool (GRP) A7 Specifications ispLSI 2032E Functional Block Diagram Figure 1. ispLSI 2032E Functional Block Diagram GOE 0 Output Routing Pool (ORP) Output Routing Pool (ORP) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TDO/IN 1 A0 A7 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16 A1 Input Bus A2 A5 A3 A4 TMS BSCAN Y0 Y1* TCK/Y2 Notes: *Y1 and RESET are multiplexed on the same pin CLK 0 CLK 1 CLK 2 Input Bus Global Routing Pool (GRP) A6 0139/2032E programmed to be a combinatorial input, output or bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. By connecting the VCCIO pins to a common 5V or 3.3V power supply, I/O output levels can be matched to 5V or 3.3V compatible voltages. When connected to a 5V supply, the I/O pins provide PCI-compatible output drive (48-pin device only). Eight GLBs, 32 I/O cells, two dedicated inputs and two ORPs are connect.


2032-6375-00 2032E 2032VE


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