2064VL

ispLSI 2064VL 2.5V In-System Programmable SuperFAST™ High Density PLD Features SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 and 32 I/O Pin Versions, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2064V and 2064VE Devices 2.5V LOW VOLTAGE 2064 ARCHITECTURE — Interfaces with Standard 3.3V TTL Devices (Inputs and I/Os are 3.3V Tolerant) — 60 mA Typical Active Current HIGH-PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 165MHz Maximum Operating Frequency — tpd = 5.5ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE Input Bus ® Functional Block Diagram Output Routing Pool (ORP) B7 B6 B5 B4 A0 Output Routing Pool (ORP) Input Bus A2 GLB Logic Array D Q D Q B1 D Q A3 A4 A5 A6 A7 B0 Output Routing Pool (ORP) Input Bus 0139A/2064VL Des...