CY7C1049

049 PRELIMINARY CY7C1049 512K x 8 Static RAM Features High speed —t AA = 15 ns Low active power — 1210 mW (max.) Low CMOS standby power (Commercial L version) — 2.75 mW (max.) 2.0V Data Retention (400 µW at 2.0V retention) Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking chip enable (CE) and output enable (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state w hen the de vice is de selected (C E HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049 is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. Functional Description The CY7C1049 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 V...