Document
DS0102 Revision 17
IGLOO PLUS Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Configurable Hold Previous State, Tristate, HIGH, or LOW State
per I/O in Flash*Freeze Mode
• Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode
Feature Rich
• 30 k to 125 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 212 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
In-System Programming (ISP) and Security
•
ISP Using On-Chip (AES) Decryption via
J1T2A8G-B(iItEEAEdv1a5n3c2e–dcoEmnpclriyapntti)o†n
Standard
• FlashLock® Designed to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • BIGaLnOk-OS®elePcLtUabSleDeIv/OicesVoltages—4 Banks per Chip on All • Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V • Selectable Schmitt Trigger Inputs • Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V • Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Small-Footprint Packages across the IGLOO
PLUS Family
Clock Conditioning Circuit (CCC) and PLL†
• Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except ×18)†
Table 1 • IGLOO PLUS Product Family
IGLOO PLUS Devices
AGLP030
AGLP060
AGLP125
System Gates
30,000
60,000
125,000
Typical Equivalent Macrocells
256 512 1,024
VersaTiles (D-flip-flops)
792
1,584
3,120
Flash*Freeze Mode (typical, µW)
5 10 16
RAM Kbits (1,024 bits)
– 18 36
4,608-Bit Blocks
–48
Secure (AES) ISP
– Yes Yes
FlashROM Kbits Integrated PLL in CCCs 1 VersaNet Globals 2
111 –11 6 18 18
I/O Banks
444
Maximum User I/Os
120 157 212
Package Pins CS VQ
CS201, CS289 VQ128
CS201, CS289 VQ176
CS281, CS289
Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.
† The AGLP030 device does not support this feature.
December 2015 © 2015 Microsemi Corporation
I
IGLOO PLUS Low Power Flash FPGAs
I/Os Per Package 1
IGLOO PLUS Devices
AGLP030
AGLP060
AGLP125
Package
Single-Ended I/Os
CS201
120 157
–
CS281
– – 212
CS289
120 157 212
VQ128
101 –
–
VQ176
– 137 –
Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of singleended user I/Os available is reduced by one.
Table 2 • IGLOO PLUS FPGAs Package Size Dimensions
Package
CS201
CS281
Length × Width (mm/mm)
8×8
10 × 10
Nominal Area (mm2)
64 100
Pitch (mm)
0.5 0.5
Height (mm)
0.89 1.05
CS289 14 × 14
196 0.8 1.20
VQ128 14 × 14
196 0.4 1.0
VQ176 20 × 20
400 0.4 1.0
IGLOO PLUS Device Status
IGLOO PLUS Device AGLP030 AGLP060 AGLP125
Status Production Production Production
II Revision 17
IGLOO PLUS Ordering Information
IGLOO PLUS Low Power Flash FPGAs
AGLP125
V2 _ CS
G
289
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +85°C junction temperature) I = Industrial (–40°C to +100°C junction temperature)
PP = Pre-Production ES = Engineering Sample (room temperature only)
Security Feature
Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
Package Type G= RoHS-Compliant Packaging
Supply Voltage
CS = Chip Scale Package (0.5 mm and 0.8 mm pitches) VQ = Very Thin Quad Flat Pack (0.4 mm pitch)
2 = 1.2 V to 1.5 V 5 = 1.5 V only
Part Number
AGLP030 = 30,000 System Gates AGLP060 = 60,000 System Gates AGLP125 = 125,000 System Gates
.