Document
DS1628 DS3628 Octal TRI-STATE MOS Drivers
February 1986
DS1628 DS3628 Octal TRI-STATE MOS Drivers
General Description
The DS1628 DS3628 are octal Schottky memory drivers with TRI-STATE outputs designed to drive high capacitive loads associated with MOS memory systems The drivers’ output (VOH) is specified at 3 4V to provide additional noise immunity required by MOS inputs A PNP input structure is employed to minimize input currents The circuit employs Schottky-clamped transistors for high speed A NOR gate of two inputs DIS1 and DIS2 controls the TRI-STATE mode
Features
Y Y Y Y
Y Y
High speed capabilities Typical 5 ns driving 50 pF 8 ns driving 500 pF TRI-STATE outputs High VOH (3 4V min) High density Eight drivers and two disable controls for TRI-STATE in a 20-pin package PNP inputs reduce DC loading on bus lines Glitch-free power up down
bs ol
TL F 5875–1
(Equivalent Input Output Circuit)
Truth Table
DIS 1 H H X L L
Disable Input
Input X X X H L
Output Z Z Z L H
O
H X H L L
H e high level L e low level X e don’t care Z e high impedance (off)
C1995 National Semiconductor Corporation TL F 5875
DIS 2
TRI-STATE is a registered trademark of National Semiconductor Corp
et
Top View
TL F 5875– 2
Order Number DS1628J DS3628J DS3628N See NS Package Number J20A or N20A
Typical Application
e
Dual-In-Line Package
TL F 5875 –3
RRD-B30M115 Printed in U S A
Schematic and Connection Diagrams
http://www.Datasheet4U.com
Absolute Maximum Ratings (Note 1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Storage Temperature Range Maximum Power Dissipation at 25 C Cavity Package Molded Package Lead Temperature (Soldering 10 seconds) 7 0V 7 0V
b 1 5V b 65 C to a 150 C
Operating Conditions
Supply voltage (VCC) Temperature (TA) DS1628 DS3628 Min 45
b 55
Max 55
a 125 a 70
Units V C C
0
1667 mW 1832 mW 300 C
Derate cavity package 11 1 mW C above 25 C derate molded package 14 7 mW C above 25 C
Electrical Characteristics (Notes 2
Symbol VIN(1) VIN(0) IIN(1) IIN(0) VCLAMP VOH VOL VOH VOL IID IOD Hi-Z ICC Parameter Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Input Clamp Voltage Logical ‘‘1’’ Output Voltage (No Load) Logical ‘‘0’’ Output Voltage (No Load) Logical ‘‘1’’ Output Voltage (With Load) Logical ‘‘0’’ Output Voltage (With Load) Logical ‘‘1’’ Drive Current Logical ‘‘0’’ Drive Current Power Supply Current
3) Conditions Min 20 08 40 Typ Max Units V V 01 mA V
VCC e 5 5V VIN e 5 5V VCC e 5 5V VIN e 5 5V VCC e 4 5V IIN e b18 mA VCC e 4 5V IOH e b10 mA VCC e 4 5V IOL e 10 mA
et
DS1628 34 43 DS3628 DS3628 DS3628 35 43 DS1628 0 25 39 04 0 25 39 0 35 DS1628 25 27 DS1628 DS3628 0 35
b 150
VCC e 4 5V IOH e b1 0 mA VCC e 4 5V IOL e 20 mA
bs ol
VCC e 4 5V VOUT e 0V (Note 6) VCC e 4 5V VOUT e 4 5V (Note 6) VCC e 5 5V VOUT e 0 4V to 2 4V DIS1 or DIS2 e 2 0V
b 40
TRI-STATE Output Current
One DIS Input e 3 0V All Other Inputs e X Outputs at Hi-Z
DIS1 DIS2 e 0V Others e 3V Outputs on All Inputs e 0V Outputs Off TA e 25 C) (Note 6)
Switching Characteristics (VCC e 5V
Symbol tS a b tS b a tF Parameter
Conditions
O
Storage Delay Negative Edge Storage Delay Positive Edge Fall Time tR tZL tZH Rise Time Delay from Disable Input to Logical ‘‘0’’ Level (from High Impedance State) Delay from Disable Input to Logical ‘‘1’’ Level (from High Impedance State)
(Figure 1 ) (Figure 1 ) (Figure 1 ) (Figure 1 ) CL e 50 pF to GND CL e 50 pF to GND 2
CL e 50 pF CL e 500 pF CL e 50 pF CL e 500 pF CL e 50 pF CL e 500 pF CL e 50 pF CL e 500 pF RL e 2 kX to VCC (Figure 2 ) RL e 2 kX to GND (Figure 2 )
e
b 180 b0 7 b 400 b1 2
mA V V V V V V V
05
mA mA 40 120 100 50 mA mA mA mA
150 01 90 70 25
Min
Typ 40 65 42 65 42 19 52 20 19 13
Max 50 80 50 80 60 22 70 24 25 20
Units ns ns ns ns ns ns
Switching Characteristics
Symbol tLZ tHZ Parameter
(Continued) (VCC e 5V TA e 25 C) (Note 6) Conditions CL e 50 pF to GND CL e 50 pF to GND RL e 400X to VCC (Figure 3 ) RL e 400X to GND (Figure 3 ) Min Typ 18 85 Max 25 15 Units ns ns
Delay from Disable Input to High Impedance State (from Logical ‘‘0’’ Level) Delay from Disable Input to High Impedance State (from Logical ‘‘1’’ Level)
AC Test Circuits and Switching Time Waveforms
tS a b tSb a tr tf
TL F 5875– 5
TL F 5875– 4
FIGURE 1 tZH tZL
bs ol
TL F 5875– 6 TL F 5875– 7
et
TL F 5875– 8
FIGURE 2 tLZ
tHZ
O
TL F 5875– 9 TL F 5875– 10
FIGURE 3
Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 Unless otherwise specified min max limits apply across the b 55 C to .