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MEC1322 Dataheets PDF



Part Number MEC1322
Manufacturers Microchip
Logo Microchip
Description Keyboard and Embedded Controller
Datasheet MEC1322 DatasheetMEC1322 Datasheet (PDF)

MEC1322 Keyboard and Embedded Controller for Notebook PC Product Features • ARM® Cortex®-M4 Processor Core - 32-Bit ARM v7-M Instruction Set Architecture - Hardware Floating Point Unit (FPU) - Single 4GByte Addressing Space (Von Neumann Model) - Little-Endian Byte Ordering - Bit-Banding Feature Included - NVIC Nested Vectored Interrupt Controller - Up to 240 Ind ividually-Vectored Interrupt Sources Supported - 8 Levels of Priority, Individually Assignable By Vector - Chip-Level Interrupt Aggrega.

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MEC1322 Keyboard and Embedded Controller for Notebook PC Product Features • ARM® Cortex®-M4 Processor Core - 32-Bit ARM v7-M Instruction Set Architecture - Hardware Floating Point Unit (FPU) - Single 4GByte Addressing Space (Von Neumann Model) - Little-Endian Byte Ordering - Bit-Banding Feature Included - NVIC Nested Vectored Interrupt Controller - Up to 240 Ind ividually-Vectored Interrupt Sources Supported - 8 Levels of Priority, Individually Assignable By Vector - Chip-Level Interrupt Aggregator supported, to expand number of interrupt sources or reduce number of vectors • 8042 Style Host Interface - Mailbox Registers Interface - Forty-three 8-Bit scratch registers - Two Register Mailbox Command Interface - Two Register SMI Sour ce Interface - System Tick Timer - Complete ARM-Standard Debug Support - JTAG-Based DAP Por t, Comprised of SWJ-DP and AHB-AP Debugger Access Functions - Full DWT Hardware Functionality: 4 Data Watchpoints and Execu tion Monitoring - Full FPB H ardware Breakpoint F unctionality: 6 Execution Breakpoints and 2 Literal ( Data) Breakpoints - Comprehensive ARM-Standard Trace Support - Full DWT Hardware Trace Functionality for Watchpoint and Per formance Monitoring - Full ITM Hardware Trace Functionality for Instrumented Firmware Support and Profiling - Full ETM H ardware Trace Functionality for Instruction Trace - Full TPIU Functionality for Trace Output Communication • Two ACPI Embedded Controller Interface - 1 or 4 Byte Data transfer capable • ACPI Power Management Interface - SCI Event-Generating Functions • Embedded Memory Interface - Host Serial IRQ Source - Provides Two Windows to On-Chip SRAM for Host Access • Two Register Mailbox Command Interface • Battery Backed (VCC0/VBAT) Resources - Power Fail Register - Power-Fail Status Register - Battery backed 64 byte memory • Real Time Clock (RTC) - VCC0 (VBAT) Powered - 32KHz Crystal Oscillator - 32KHz Clock output available under VCC1 power - Time-of-Day and Calendar Registers - Programmable Alarms - Supports Leap Year and Daylight Savings Time • Hibernation Timers • General Purpose Analog to Digital Converter - 10-bit conversion precision - 10-bit conversion per channel is completed in less than 12us - 5 ADC channels - 10-bit Conversion with 2.9mV r esolution - 0 to 3.3 VDC Conversion Range • 128K SRAM (Code or Data) - 96K Optimized for Code - 32K Optimized for Data • LPC Interface - Supports LPC Bus frequencies of 19MHz to 33MHz - LPC I/O Cycles Decoded - LPC Memory Cycles Decoded - Clock Run Support -S erial IRQ - ACPI SCI interface - SMI# output • Two SPI Memory Interfaces - 3-pin Full Duplex serial communication interface - Two Private and Two Shared Chip Selects - DMA Support • • • • - Optional continuous sampling at a programmable rate - Internal Analog Voltage Reference (3.0V +/1%) Watch Dog Timer Four Programmable 16-bit and Two 32-bit Timers - Wake-capable Auto-reloading Timers Four Independent Hardware Driven PS/2 Ports - Fully functional on Main and/or Suspend Power - PS/2 Edge Wake Capable Four Programmable Pulse-Width Modulator Outputs - Independent Clock Rates - 16-Bit Duty Cycle Granularity - Operational in both Full on and Standby modes  2014 Microchip Technology Inc. DS00001733A-page 1 http://www.Datasheet4U.com MEC1322 • Four EC-based SMBus 2.0 Host Controllers - Allows Master or Dual Slave Operation - Controllers are Fully Operational on Standby Power - DMA-driven I2C Network Layer Hardware -I 2C Datalink Compatibility Mode - Multi-Master Capable - Supports Clock Stretching - Programmable Bus Speeds - 400 KHz Fast-mo de Capable - 1 Mbps Fast-mode Plus Ca pable Description The MEC1322 incorporates a high-performance 32-bit ARM® Cortex®-M4 embedded microcontroller with 128 Kilobytes of SRAM and 32 Ki lobytes of Boot ROM. It communicates with the system host using the Intel® Low Pin Count (LPC) bus. The MEC13 22 has two SPI memo ry interfaces that allow the EC to read its code from external SPI fl ash memory: private SPI a nd/or sha red SPI. T he Sha red SPI interface a llows for EC co de to be stored in a shared SPI chip along with the system BIOS. The private SPI me mory interface provi des for a dedi cated SPI flash that is only accessible by the EC. The MEC132 2 provi des sup port fo r l oading EC co de from the private or shared SPI flash device on a VCC1 power-on. Before executing the EC code loaded from a SPI Flash Device, the MEC1322 validates the EC code using a digi tal signature encoded according to PKCS #1. T he sig nature use s R SA-2048 e ncryption a nd SHA-256 hashing. This provides automated detection of invalid EC code that may be a result of malicious or accidental corruption. It occurs before each boot of the host processor, thereby ensuring a HW based root of trust no t ea sily th warted via ph ysical repl acement attack. The MEC1322 is directly powered by two separate suspend supply planes (VBAT and VCC1) and senses the runtime power plane (VCC) to provide “Instant On” and system .


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