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IS67WV51216DBLL Dataheets PDF



Part Number IS67WV51216DBLL
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description 8Mb LOW VOLTAGE ULTRA LOW POWER PSEUDO CMOS STATIC RAM
Datasheet IS67WV51216DBLL DatasheetIS67WV51216DBLL Datasheet (PDF)

hgihwol D wol D IS66WV51216DALL IS66/67WV51216DBLL 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM JULY 2011 FEATURES • High-speed access time: – 70ns (IS66WV51216DALL, IS66/67WV51216DBLL) – 55ns (IS66/67WV51216DBLL) • CMOS low power operation • Single power supply – Vdd = 1.7V-1.95V (IS66WV51216 ALL) – Vdd = 2.5V-3.6V (IS66/67WV51216 BLL) • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Lead-free.

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hgihwol D wol D IS66WV51216DALL IS66/67WV51216DBLL 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM JULY 2011 FEATURES • High-speed access time: – 70ns (IS66WV51216DALL, IS66/67WV51216DBLL) – 55ns (IS66/67WV51216DBLL) • CMOS low power operation • Single power supply – Vdd = 1.7V-1.95V (IS66WV51216 ALL) – Vdd = 2.5V-3.6V (IS66/67WV51216 BLL) • Three state outputs • Data control for upper and lower bytes • Industrial temperature available • Lead-free available FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS66WV51216DALL and IS66/67WV51216DBLL are high-speed, 8M bit static RAMs organized as 512K words by 16 bits. It is fabricated using ISSI's high- performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is (deselected) or when CS1 is , CS2 is and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS66WV51216DALL and IS66/67WV51216DBLL are packaged in the JEDEC standard 48-ball mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II). The device is aslo available for die sales. A0-A18 DECODER 512K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CS2 CS1 OE CONTROL WE CIRCUIT UB LB Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 06/28/2011 1 http://www.Datasheet4U.com IS66WV51216DALL IS66/67WV51216DBLL PIN CONFIGURATIONS: 48-Ball mini BGA (6mm x 8mm) 1 23 45 6 A LB OE A0 A1 A2 CS2 B I/O8 UB A3 A4 CS1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD` E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC 44-Pin TSOP (Type II) A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PIN DESCRIPTIONS A0-A18 I/O0-I/O15 CS1, CS2 OE WE LB UB NC Vdd GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground 44 A5 43 A6 42 A7 41 OE 40 UB 39 LB 38 I/O15 37 I/O14 36 I/O13 35 I/O12 34 GND 33 VDD 32 I/O11 31 I/O10 30 I/O9 29 I/O8 28 A18 27 A8 26 A9 25 A10 24 A11 23 A17 2 Integrated Silicon Solution, Inc. — www.issi.com Rev.  A 06/28/2011 noitailaitin prewo iD iD iD iD D D D D bsbs bsbs bsbs IS66WV51216DALL IS66/67WV51216DBLL TRUTH TABLE Mode Not Selected Output Disabled Read Write WE CS1 CS2 OE LB UB XHXXXX XXLXXX XXXXHH HLHHL X HLHHX L HLHL LH HLHLHL HLHL L L L LHXLH L LHXHL L LHXL L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z out High-Z High-Z out out out n High-Z High-Z n nn Vdd Current I 1, I 2 I 1, I 2 I 1, I 2 Icc Icc Icc Icc Note: CS2 input signal pin is only available for 48-ball mini BGA package parts. CS2 input is internally enabled for 44-pin TSOP-II package parts. OPERATING RANGE (Vdd) Range Industrial Automotive, A1 Automotive, A2 Ambient Temperature –40°C to +85°C –40°C to +85°C –40°C to +105°C IS66WV51216DALL (70ns) 1.7V - 1.95V – – IS66WV51216DBLL (55ns, 70ns) 2.5V - 3.6V – – IS67WV51216DBLL (55ns, 70ns) – 2.5V - 3.6V 2.5V - 3.6V P -U I z IS66WV512616DALL/DBLL a.


IS66WV51216DBLL IS67WV51216DBLL ISL6364


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