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Effect Transistor. P75N02LDG Datasheet

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Effect Transistor. P75N02LDG Datasheet






P75N02LDG Transistor. Datasheet pdf. Equivalent




P75N02LDG Transistor. Datasheet pdf. Equivalent





Part

P75N02LDG

Description

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Manufacture

Niko

Datasheet
Download P75N02LDG Datasheet


Niko P75N02LDG

P75N02LDG; NIKO-SEM N-Channel Logic Level Enhancem ent Mode Field Effect Transistor P75N0 2LDG TO-252 (DPAK) Lead-Free D PRODUCT SUMMARY V(BR)DSS 25 RDS(ON) 5m£[ ID 7 5A 1. GATE 2. DRAIN 3. SOURCE G S ABS OLUTE MAXIMUM RATINGS (TC = 25 °C Unle ss Otherwise Noted) PARAMETERS/TEST CON DITIONS Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Aval anche Current Avalan.


Niko P75N02LDG

che Energy Repetitive Avalanche Energy P ower Dissipation 2 1 SYMBOL VGS ± LI MITS 20 75 50 170 60 140 5.6 60 32.75 - 55 to 150 UNITS V TC = 25 °C TC = 10 0 °C ID IDM IAR A L = 0.1mH L = 0.0 5mH TC = 25 °C TC = 100 °C EAS EAR P D Tj, Tstg TL 275 mJ W Operating Jun ction & Storage Temperature Range Lead Temperature ( /16” from case for 10 s ec.) THERMAL RESISTANCE R.


Niko P75N02LDG

ATINGS THERMAL RESISTANCE Junction-to-Ca se Junction-to-Ambient Case-to-Heatsink 1 2 1 °C SYMBOL RθJC RθJA RθCS TYPICAL MAXIMUM 2.3 62.5 UNITS °C / W 0.6 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1 ¢H ELECTRICAL CHARACTERISTICS (TC = 2 5 °C, Unless Otherwise Noted) PARAMETE R SY MBOL TEST CONDITIONS STATIC Drain- Source Breakdown Voltage Ga.



Part

P75N02LDG

Description

N-Channel Logic Level Enhancement Mode Field Effect Transistor

Manufacture

Niko

Datasheet
Download P75N02LDG Datasheet




 P75N02LDG
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P75N02LDG
TO-252 (DPAK)
Lead-Free
PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
25 5m
ID
75A
D
G
1. GATE
2. DRAIN
3. SOURCE
S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current1
TC = 25 °C
TC = 100 °C
Avalanche Current
Avalanche Energy
Repetitive Avalanche Energy2
L = 0.1mH
L = 0.05mH
Power Dissipation
TC = 25 °C
TC = 100 °C
Operating Junction & Storage Temperature Range
Lead Temperature (1/16” from case for 10 sec.)
VGS ±
ID
IDM
IAR
EAS
EAR
PD
Tj, Tstg
TL 275
LIMITS
20
75
50
170
60
140
5.6
60
32.75
-55 to 150
UNITS
V
A
mJ
W
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction-to-Case
RθJC
Junction-to-Ambient
RθJA
Case-to-Heatsink
RθCS
1Pulse width limited by maximum junction temperature.
2Duty cycle 1
TYPICAL
0.6
MAXIMUM
2.3
62.5
UNITS
°C / W
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
PARAMETER SY
MBOL
TEST CONDITIONS
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
V(BR)DSS
VGS(th)
IGSS V
IDSS
STATIC
VGS = 0V, ID = 250µA
VDS = VGS, ID = 250µA
DS = 0V, VGS = ±20V
VDS = 20V, VGS = 0V
VDS = 20V, VGS = 0V, TJ = 125 °C
LIMITS
UNIT
MIN T YP MAX
25
1 1.5
3
±250
25
250
V
nA
µA
1 SEP-02-2004
http://www.Datasheet4U.com





 P75N02LDG
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P75N02LDG
TO-252 (DPAK)
Lead-Free
On-State Drain Current1
Drain-Source On-State
Resistance1
Forward Transconductance1
ID(ON)
RDS(ON)
gfs V
VDS = 10V, VGS = 10V
VGS = 10V, ID = 30A
VGS = 7V, ID = 24A
DS = 15V, ID = 30A
70
5
6
16
7
8
DYNAMIC
Input Capacitance
Ciss
5000
Output Capacitance
Coss VGS = 0V, VDS = 15V, f = 1MHz
1800
Reverse Transfer Capacitance
Total Gate Charge2
Gate-Source Charge2
Gate-Drain Charge2
Turn-On Delay Time2
Rise Time2
Turn-Off Delay Time2
Fall Time2
Crss
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
VDS = 0.5V(BR)DSS, VGS = 10V,
ID = 35A
VDS = 15V, RL = 1
ID 30A, VGS = 10V, RGS = 2.5
800
140
40
75
7
7
24
6
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
Pulsed Current3 I
Forward Voltage1 V
IS
SM
SD I
F = IS, VGS = 0V
75
170
1.3
Reverse Recovery Time
trr
37
Peak Reverse Recovery Current
IRM(REC)
IF = IS, dlF/dt = 100A / µS
200
Reverse Recovery Charge
Qrr
1Pulse test : Pulse Width 300 µsec, Duty Cycle 2 .
2Independent of operating temperature.
3Pulse width limited by maximum junction temperature.
0.043
A
m
S
pF
nC
nS
A
V
nS
A
µC
REMARK: THE PRODUCT MARKED WITH “P75N02LDG”, DATE CODE or LOT #
Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name.
2 SEP-02-2004





 P75N02LDG
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P75N02LDG
TO-252 (DPAK)
Lead-Free
TO-252 (DPAK) MECHANICAL DATA
Dimension
A
B
C
D
E
F
G
mm
Min. T
yp.
9.35 10.4
2.2 2.4
0.45
0.89
1.5
0.45 0.69
0.03 0.23
5.2 6.2
Dimension
Max.
H
I
0.6 J 5.2
K
L 0.5
M
N
Min. T
0.89
6.35
0.6
3.96
mm
yp.
4.57
Max.
2.03
6.80
5.5
1
0.9
5.18
A
HG
K
3 SEP-02-2004



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