P75N02LDG

NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P75N02LDG TO-252 (DPAK) Lead-Free D PRODUCT SUMMARY V(BR)DSS 25 RDS(ON) 5m£[ ID 75A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Avalanche Current Avalanche Energy Repetitive Avalanche Energy Power Dissipation 2 1 SYMBOL VGS ± LIMITS 20 75 50 170 60 140 5.6 60 32.75 -55 to 150 UNITS V TC = 25 °C TC = 100 °C ID IDM IAR A L = 0.1mH L = 0.05mH TC = 25 °C TC = 100 °C EAS EAR PD Tj, Tstg TL 275 mJ W Operating Junction & Storage Temperature Range Lead Temperature ( /16” from case for 10 sec.) THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient Case-to-Heatsink 1 2 1 °C SYMBOL RθJC RθJA RθCS TYPICAL MAXIMUM 2.3 62.5 UNITS °C / W 0.6 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1¢H ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SY MBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current V(BR)DSS VGS(th) IGSS V IDSS VGS = 0V, ID = 250µA VDS = VGS, ID = 250µA DS LIMITS UNIT MIN T YP MAX 25 1 1.5 3 ±250 25 250 V nA µA = 0V, VGS = ±20V VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125 °C 1 SEP-02-2004 http://www.Datasheet4U.com NIKO-SEM 1 N-Channel Logic Level Enhancement Mode Field Effect Trans...