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H5TQ2G83DFR-xxL Dataheets PDF



Part Number H5TQ2G83DFR-xxL
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 2Gb DDR3 SDRAM
Datasheet H5TQ2G83DFR-xxL DatasheetH5TQ2G83DFR-xxL Datasheet (PDF)

2Gb DDR3 SDRAM 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G83DFR-xxC H5TQ2G63DFR-xxC H5TQ2G83DFR-xxI H5TQ2G63DFR-xxI H5TQ2G83DFR-xxJ H5TQ2G63DFR-xxJ H5TQ2G83DFR-xxL H5TQ2G63DFR-xxL * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.1 / May. 2012 1 http://www.Datasheet4U.com Revision History Revision No. 0.01 0.02 0.03 0.04 0.05 0.06 0.07 History Preliminary version release Add temperature information in feature update operation frequen.

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2Gb DDR3 SDRAM 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G83DFR-xxC H5TQ2G63DFR-xxC H5TQ2G83DFR-xxI H5TQ2G63DFR-xxI H5TQ2G83DFR-xxJ H5TQ2G63DFR-xxJ H5TQ2G83DFR-xxL H5TQ2G63DFR-xxL * SK Hynix reserves the right to change products or specifications without notice. Rev. 1.1 / May. 2012 1 http://www.Datasheet4U.com Revision History Revision No. 0.01 0.02 0.03 0.04 0.05 0.06 0.07 History Preliminary version release Add temperature information in feature update operation frequency update IDD 1600,1866,2133 update IDD data update IDD data (x8) update Pakage Dimension (x16) - Corrected Pakage Dimension (Page 34 , 78 Balls to 96Balls) update IDD data Official Version Release Official Version Release & Add L/J Part Delete Comments regarding IDD6TC & New revised logo (Hynix to SK hynix) Draft Date July. 2011 Aug. 2011 Oct. 2011 Nov. 2011 Nov. 2011 Dec. 2011 Dec. 2011 Remark Preliminary Preliminary Preliminary Preliminary Preliminary Preliminary Preliminary 0.08 0.09 1.0 1.1 Feb.2012 Mar.2012 Apr.2012 May.2012 Page 24, all IDD specs are completed Deleted “Preliminary” Add L/J Part support Page 12/17/24 Rev. 1.1 / May. 2012 2 Description The H5TQ2G83DFR-xxC, H5TQ2G63DFR-xxC,H5TQ2G83DFR-xxI, H5TQ2G63DFR-xxI, H5TQ2G83DFRxxL,H5TQ2G63DFR-xxL,H5TQ2G83DFR-xxJ,H5TQ2G63DFR-xxJ are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES • VDD=VDDQ=1.5V +/- 0.075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average R efresh Cy cle (Tcase 0 oC~ 95 oC) o - 7.8 µs at 0 C ~ 85 oC - 3.9 µs at 85oC ~ 95 oC Commercial Temperature( 0oC ~ 85 oC) Industrial Temperature( -40oC ~ 95 oC) • JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16) • Driver strength selected by EMRS • Dynamic On Die Termination supported • Asynchronous RESET pin supported • ZQ calibration supported • TDQS (Termination Data Strobe) supported (x8 only) • Write Levelization supported • 8 bit pre-fetch * This product in compliance with the RoHS directive. Rev. 1.1 / May. 2012 3 ORDERING INFORMATION Part No. H5TQ2G83DFR-*xxC H5TQ2G83DFR-*xxI H5TQ2G83DFR-*xxL H5TQ2G83DFR-*xxJ H5TQ2G63DFR-*xxC H5TQ2G63DFR-*xxI H5TQ2G63DFR-*xxL H5TQ2G63DFR-*xxJ 128M x 16 Low Power Consumption (IDD6 Only) 256M x 8 Low Power Consumption (IDD6 Only) Normal Consumption Configuration Power Consumption Normal Consumption Temperature Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 96ball FBGA 78ball FBGA Package * xx means Speed Bin Grade OPERATING FREQUENCY Speed Grade (Marking) -G7 -H9 -PB -RD -TE Frequency [Mbps] CL5 667 667 667 CL6 800 800 800 800 800 CL7 1066 1066 1066 1066 1066 CL8 1066 1066 1066 1066 1066 1333 1333 1333 1333 1333 1333 1333 1333 1600 1600 1600 1866 1866 2133 CL9 CL10 CL11 CL12 CL13 CL14 Remark (CL-tRCD-tRP) DDR3-1066 7-7-7 DDR3-1333 9-9-9 DDR3-1600 11-11-11 DDR3-1866 13-13-13 DDR3-2133 14-14-14 * xx means Speed Bin Grade Rev. 1.1 / May. 2012 4 x8 Package Ball out (Top view): 78ball FBGA Package 1 A B C D E F G H J K L M N VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 VDD VSSQ DQ2 DQ6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 NC DQ0 DQS DQS DQ4 RAS CAS WE BA2 A0 A2 A9 A13 3 4 5 6 4 5 6 7 NU/TDQS DM/TDQS DQ1 VDD DQ7 CK CK A10/AP NC A12/BC A1 A11 A14 7 8 VSS VSSQ DQ3 VSS DQ5 VSS VDD ZQ VREFCA BA1 A4 A6 A8 8 9 VDD VDDQ VSSQ VSSQ VDDQ NC CKE NC VSS VDD VSS VDD VSS 9 A B C D E F G H J K L M N 1 2 3 A B C D E F G H J K L M N 7 8 9 (Top View: See the balls through the Package) Populated ball Ball not populated Rev. 1.1 / May. 2012 5 x16 Package Ball out (Top view): 96ball FBGA Package 1 A B C D E F G H J K L M N P R T VDDQ VSSQ VDDQ VSSQ VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 1 2 DQU5 VDD DQU3 VDDQ VSSQ DQL2 DQL6 VDDQ VSS VDD CS BA0 A3 A5 A7 RESET 2 3 DQU7 VSS DQU1 DMU DQL0 DQSL DQSL DQL4 RAS CAS WE BA2 A0.


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