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BUK9508-55A Dataheets PDF



Part Number BUK9508-55A
Manufacturers NXP
Logo NXP
Description logic level FET
Datasheet BUK9508-55A DatasheetBUK9508-55A Datasheet (PDF)

BUK95/9608-55A TrenchMOS™ logic level FET Rev. 03 — 6 May 2002 Product data 1. Description N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™ technology, featuring very low on-state resistance. BUK9508-55A in SOT78 (TO-220AB) BUK9608-55A in SOT404 (D2-PAK). 2. Features s s s s 4. Pinning information Table 1: Pin 1 Description Pinning - SOT78 and SOT404, simplified outline and symbol Simplified outline mb mb F w C ww ua s Automotive and general pu.

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BUK95/9608-55A TrenchMOS™ logic level FET Rev. 03 — 6 May 2002 Product data 1. Description N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™ technology, featuring very low on-state resistance. BUK9508-55A in SOT78 (TO-220AB) BUK9608-55A in SOT404 (D2-PAK). 2. Features s s s s 4. Pinning information Table 1: Pin 1 Description Pinning - SOT78 and SOT404, simplified outline and symbol Simplified outline mb mb F w C ww ua s Automotive and general purpose power switching: x 12 V and 24 V loads x Motors, lamps and solenoids. r e .n a [1] MBK106 3. Applications t e n 1 TrenchMOS™ technology Q101 compliant 175 °C rated Logic level compatible. ce. Symbol d g s MBB076 PD gate (g) 2 drain (d) 3 source (s) mb mounting base; connected to drain (d) 2 3 MBK116 1 2 3 SOT78 (TO-220AB) [1] It is not possible to make connection to pin 2 of the SOT404 package. 8 c T SOT404 (D2-PAK) om http://www.Datasheet4U.com ria Product availability: l Philips Semiconductors BUK95/9608-55A TrenchMOS™ logic level FET 5. Quick reference data Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions Tmb = 25 °C; VGS = 5 V Tmb =2 5 °C Tj =2 5 °C; VGS =5V ; ID =2 5A Typ 6.8 Tj = 25 °C; VGS = 4.5 V; ID =2 5A Max 55 125 253 175 8 8.5 7.5 Unit V A W °C mΩ mΩ mΩ drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter Tj =2 5 °C; VGS = 10 V; ID = 25 A 6. Limiting values Symbol Parameter VDS VDGR VGS ID drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) Conditions om [1] [2] [2] Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). 8 c T ce. ria 6.4 Min -7 -7 −55 −55 [1] [2] l Max 55 55 ±15 125 5 5 503 253 +175 +175 125 5 503 670 -7 - Unit V V V A A A A W °C °C A A A mJ IDM Ptot Tstg Tj IDR peak drain current F w C total power dissipation storage temperature junction temperature Source-drain diode PD IDRM Avalanche ruggedness [1] [2] reverse drain current (DC) peak reverse drain current EDS(AL)S non-repetitive drain-source avalanche energy Current is limited by power dissipation chip rating Continuous current is limited by package. ww r e .n a Tmb =2 5 °C Tmb =2 5 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb =2 5 °C; Figure 1 Tmb =2 5 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID =7 5A ; VDS ≤ 55 V; VGS =5V ; RGS =5 0 Ω; starting Tmb =2 5 °C ua t e n RGS = 20 kΩ Tmb =2 5 °C; VGS =5V ; Figure 2 and 3 Rev. 03 — 6 May 2002 Tmb = 100 °C; VGS =5V ; Figure 2 9397 750 09573 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data 2 of 14 Philips Semiconductors BUK95/9608-55A TrenchMOS™ logic level FET 120 Pder (%) 80 03na19 150 ID (A) 03ni52 100 40 50 Capped at 75 A due to package 0 0 50 100 150 200 Tmb (° C) 8 c T 0 25 50 75 100 ria 125 150 103 r e .n a Limit RDSon = VDS/ID ce. DC 10 Fig 1. Normalized total power dissipation as a function of mounting base temperature. t e n ua Rev. 03 — 6 May 2002 P tot P der = ---------------------- × 100 % P ° tot () 25 C VGS ≥ 4.5 V Fig 2. Continuous drain current as a function of mounting base temperature. om VDS (V) F w C ID (A) ww 102 Capped at 75 A due to package 1 ms PD 10 1 10-1 1 102 Tmb =2 5 °C; IDM single pulse. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 09573 Product data l 175 200 Tmb (ºC) 03ni50 tp = 10 µs 100 µs 10 ms 100 ms © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 3 of 14 Philips Semiconductors BUK95/9608-55A TrenchMOS™ logic level FET 7. Thermal characteristics Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Figure 4 Min Typ Max 0.59 Unit K/W thermal resistance from junction to mounting base thermal resistance from junction to ambient SOT78 SOT404 vertical in still air mounted on a printed circuit board; minimum footprint 60 50 K/W K/W Symbol Parameter 7.1 Transient thermal impedance 8 c T ce. 10-3 10-2 ria om P 1 Zth(j-mb) (K/W) δ = 0.5 0.2 10-1 0.1 0.05 0.02 10-2 r e .n a ww 10-4 ua t e n Rev. 03 — 6 May 2002 F w C single shot 10-3 PD 10-6 10-5 l δ= tp T t 03ni51 tp T 10-1 tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 09573 © Koninklijke Philips Electronics N.V. 2002. All rights reserved. Product data 4 of 14 Philips Semiconductors BUK95/9608-55A TrenchMOS™ logic level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 0.25 mA; VGS = 0 V Tj = 25 °C Tj = −55 °C5 VGS(th) gate-source threshold voltage ID = 1 mA; VDS =V GS; Figure 9 Tj =2 5 °C Tj = 175 °C Tj = −55 °C IDSS drain-source leakage current Tj =2 5 °C Tj = 175 °C IGSS RDSon gate-source leakage current drain-s.


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